Motorola Corporation

William Alexander Bucher

Scott David Blanchard

Kurt Albert Kallman

Joel Lloyd Gross

Mark Alan Kirschenmann

William Walsh

Peter David Novak

Warren P Berryman

Fredrick J Bontemps

Clay Garlen Jones

Roman S Ebert

Scott J Leahy

A base station has a processor to generate a Code Division Multiple Access ('CDMA') data frame. The CDMA data frame comprises a plurality of Basic Frames. At least one of the plurality of Basic Frames comprises a vendor-specific field. A modem transports the CDMA data frame over a Universal Mobile Telecommunications System ('UMTS')-compatible link between the base station and a remote head having a transceiver.

Method and apparatus for transporting CDMA traffic over a UMTS-compatible CPRI interface

In a data synchronizer a timing error estimator samples a received stream of digitized data symbols at the beginning, end, and a mid-point of a symbol period. These samples are used with a model that assumes that a data stream waveform should transition along a straight line between its values at optimum sampling instances, separated by the symbol period. Differences between a mid-symbol sample estimated using this straight line model and the actual mid-symbol sample are assumed to be due to a timing error. The timing error estimator performs computations on complex inputs and therefore is compatible with a wide variety of modulation types.

Data synchronizer phase detector and method of operation thereof

A method and apparatus for performing adaptive filtering in a high interference environment, such as for a radio, modem, or local area network. The adaptive filtering simultaneously provides interference excision while canceling resultant distortion in the signal caused by synthesizing the notch used to excise the interfering signal. An input signal (13) is pre-filtered (14) and the pre-filtered signal (15) is processed by a rejection filter (12) which combines weighted delayed versions of the pre-filtered signal (40, 42, 44, 46, 48, 50), weighted delayed versions of data decisions corresponding to the same delays as that used in the pre-filtered signal (60, 62, 64, 66, 68, 70), and a post filtered signal (27) to produce the filtered signal (19). The filtered signal (19) is processed by a data and coefficient estimator (18) to provide data decisions (25) and tap weight values (21, 23).

Method and apparatus for adaptive filtering in a high interference

An apparatus and accompanying method for demodulating with baseband Doppler frequency shift compensation. An RF section (20) down-converts received data communication signals (12) to baseband. A/D converters (24, 26) digitize I, Q quadrature baseband signal components. Phase (32) and frequency (50) tracking loops reside on a common digital ASIC substrate (28). A complex multiplier (30) rotates digitized baseband signals by a digitized oscillation signal, producing Doppler shift compensated signals. The phase tracking loop (32) estimates data and generates a pure phase error signal from which data modulation and Doppler shift compensation influences have been removed, which drives a frequency discriminator (52) that identifies either clockwise or counterclockwise phase rotation for each symbol (18). An integrator (54) combines identification results over a burst and a numerically controlled oscillator (56) adjusts the digitized oscillation signal frequency in a constant frequency step. This adjustment takes place once for each burst.

Demodulator with baseband doppler shift compensation and method

In a data synchronizer a timing error estimator samples a received data stream and generates a clock to provide optimal sampling of the data stream, and a lock detector monitors the clock and received data stream to provide an indication of whether optimal sampling has been achieved. The lock detector processes differences between delayed versions of the input which are sampled based upon the clock timing. These sampled differences are then processed by a non-linear circuit to provide a lock signal indication which, when compared to a predetermined threshold signal, is used to provide optimal sampling indication. The lock detector performs computations on real and complex inputs and therefore is compatible with a wide variety of modulation types. The lock detector can be implemented in either analog or digital circuits, making it applicable to a broad range of data synchronizer applications.

Data synchronizer lock detector and method of operation thereof

In a communication system (10), a receiving node (14) estimates bit error rate (BER) and the accuracy of the BER estimate based upon a single burst of a data communication signal (12). An appropriate decision rule (92) is selected (90) in response to the BER accuracy estimate. Different decision rules (92) are available to bias different decisions to favor desired outcomes. The bias is configured in response to the BER accuracy estimate. The selected decision rule (92) is evaluated (96) in view of an estimated BER. In response to this evaluation, a transmitting node (14) may be instructed (104) to increase or decrease its transmit power level. In addition, the BER may be measured, and the measurement used to verify the appropriateness of the decision rules (92).

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Tempe, AZ, United States of America

William Alexander Bucher