Motorola Corporation

Arm Limited

William Adam Hohl

Joseph Charles Circello

David Vivian Jaggar

James Stroman Hall

Apparatus for processing data is provided, said apparatus comprising: a main processor responsive to main processor instructions within a stream of instructions input to said main processor to perform main processor operations; a coprocessor coupled to said main processor via a coprocessor interface CP and responsive to coprocessor instructions MCR, MRC within said stream of instructions to perform coprocessor operations; wherein said coprocessor is a debug coprocessor operable to at least partially control generation of diagnostic data for debugging said apparatus for processing data and said coprocessor instructions are debug coprocessor instructions that control operation of said debug coprocessor. Using a debug mechanism in the form of a debug coprocessor reduces the impact of the debug mechanism upon normal operation.

Debug mechanism for data processing systems

Apparatus for processing data is provided, said apparatus comprising: a main processor ; an instruction transfer register ITR for holding a data processing instruction and accessible via a first serial scan chain SC ; a data transfer register DTR for holding a data value and accessible via a second serial scan chain SC ; debug logic for controlling said main processor , said instruction transfer register ITR and said data transfer register DTR such that a data processing instruction held within said instruction transfer register ITR is passed a plurality of times to said main processor for execution upon a sequence of data values scanned into or from said data transfer register via said second serial scan chain. In this way operational speed of the debug mode is increased since the data processing instruction only needs to be transferred once.

Executing multiple debug instructions

Apparatus for processing data is provided, said apparatus comprising: a main processor,driven by a main processor clock signal clk at a main processor clock frequency; debug logic,at least a portion,of which is driven by a debug clock signal tck at a debug clock frequency, said debug clock frequency being different to said main processor clock frequency and said main processor clock signal clk being asynchronous with said debug clock signal tck; and an instruction transfer register ITR into which a data processing instruction may be transferred by said debug logic,and from which said data processing instruction may be read by said main processor,wherein when switched from a normal mode to a debug mode said main processor,continues to be driven by said main processor clock signal clk executing no-operation instructions until a data processing instruction is present within said instruction transfer register ITR and said debug logic,triggers said main processor to read and execute said data processing instruction whilst still driven by said main processor clock signal clk. This arrangement allows debug instructions to be executed at full speed whilst avoiding the need to switch clock speeds and provide a synchronisation mechanism.

Executing debug instructions

A central processing unit (2) and a debug module (10) execute concurrent operations without requiring a data processor (3) to operate in a special debug mode. The use of a bus (25) to communicate data, address, and control information between a core (9) and debug module (10) allows debug module (10) to have access the same internal registers and memory locations as central processing unit (2). While debug module (10) and central processing unit (2) both have the ability to access the same internal registers and memory locations, central processing unit (2) may not modify a value stored in a plurality of breakpoint registers (50) when an Inhibit Processor Writes to Debug Registers (IPW) bit in a CSR (FIG. 8) of a plurality of control registers (40) is set. The IPW bit may only be modified by a command provided by an external development system (7).

Data processing system for controlling execution of a debug function and

A central processing unit (2) and a debug module (10) execute concurrent operations without requiring a data processor (3) to operate in a special debug mode. The use of a bus (25) to communicate data, address, and control information between a core (9) and debug module (10) allows debug module (10) to have access the same internal registers and memory locations as central processing unit (2). While debug module (10) and central processing unte (2) both have the ability to access the same internal registers and memory locations, central processing unit (2) may not modify a value stored in a plurality of breakpoint registers (50) when an Inhibit Processor Writes to Debug Registers (IPW) bit in a CSR (FIG. 8) of a plurality of control registers (40) is set. The IPW bit may only be modified by a command provided by an external development system (7).

A data processor (3) executes a debug operation by minimally intruding on the real time operation of the data processor and without halting the data processor. The data processor implements a control register (40) which stores trigger response value for determining a function executed by the data processor when a breakpoint signal is asserted. The trigger response values indicates whether a central processing unit (2) of the data processor executes a special debug exception processing routine or suspends operation when the breakpoint signal is asserted.

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Pflugerville, TX, United States of America

William Adam Hohl