Xilinx, Inc.

Other

William A Wilkie

Thomas A Kean

Christopher H Dick

Charles R Erickson

Philip M Freidin

Richard Lewis Walke

Ben J Jones

David I Lawrie

Elizabeth R Cowie

A modem includes an outer transceiver including a soft decision forward error correction (SD-FEC) circuit, wherein the SD-FEC circuit is hardwired and programmable to perform at least one of encoding or decoding data using a code type selected from a plurality of different code types, and an inner transceiver coupled to the SD-FEC circuit, wherein the inner transceiver is implemented in programmable circuitry.

Software defined modem

A decoder in a device receiving data having an error correction code is described. The decoder comprises a memory storing program code having instructions including control signals for decoding an error correction code; an address generator coupled to the memory, the address generator updating an address coupled to the memory for generating a next control signal; and a data processing circuit coupled to receive an instruction from the memory and further coupled to receive syndrome data, the data processing circuit generating error correction values. A method for decoding data having an error correction code is also disclosed.

Decoder in a device receiving data having an error correction code and a method of decoding data

A circuit for a multi-channel add-compare-select unit is disclosed. The circuit includes a compare unit and a datapath. The datapath is coupled to the compare unit, and includes a number of adder units, a selection unit (which is coupled to the adder units), and a number of clocked storage stages.

Method and system for a multi-channel add-compare-select unit

Method and apparatus for coding and, more particularly, for Reed-Solomon encoding and decoding with puncturing are described. At least one core is generated responsive to a puncture pattern input provided to a core generator. The core may be an encoder core or a decoder core, or a combination thereof such as a CODEC. For this generation, the puncture pattern input, including puncture patterns, are for a polynomial generator. The at least one core is configured to provide encoding or decoding, as applicable, responsive to the puncture patterns for which it was configured as generated with the core generator.

Encoding and decoding with puncturing

A configuration structure for a field programmable gate array (FPGA) allows a user to reconfigure or partly reconfigure the FPGA from within the FPGA, allows an addressable configuration memory to be addressed in parallel through a set of address and data or through a serial interface. Signals such as chip-enable and other control signals can be modified by user logic so that data loaded through a serial interface pin is entered into an addressed portion of configuration memory. The configuration memory programs not only the internal circuitry accessed by the user but also a programmable switch for directing signals between external pins, configuration memory control lines, and a serial data interface. Providing both parallel and serial interfaces allows a programmable switch which is initially configured to connect its related pad or pads to configuration control lines such as a chip enable line or a serial data input line to later be configured to connect an internally generated signal or signals to the line or lines and thus override any external signal which would have been connected to that line or lines.

FPGA with parallel and serial user interfaces

In an FPGA having registers which are part of a user's logic functions and a configuration memory which is read and written through an addressing structure, a register protect circuit controllably protects the contects of these user logic registers from being modified by signals from the user's logic, allows these registers to be written by a microprocessor through the configuration memory addressing structure, and allows both the user's registers and lines which provide combinational signals to be read by a microprocessor through the configuration memory addressing structure.

Register protection structure for FPGA

The present invention provides a means and method of generating a long error checking polynomial remainder having the ability to detect errors with high reliability and inserting only a subset of the polynomial remainder periodically into a data stream, then at the receiving end recalculating the polynomial remainder and checking the inserted subset for errors. The polynomial has the property that the current remainder value is a function of all data previously transmitted in a transmission session. The subset transmitted also preferably has this property. A longer subset of the polynomial remainder, or the full polynomial remainder, may be inserted less frequently, and is preferably sent and tested at the end of the transmission session. Both serial and parallel data streams may be checked.

Growing community of inventors

Edinburgh, United Kingdom

William A Wilkie