Texas Instruments Corporation

Other

Microtune (texas), Inc.

William A White

Albert H Taddiken

Geoffrey C Dawe

Christopher T Chang

Mooshi R Namordi

David A Whitmire

Horizontal ground boring apparatus

An underground horizontal boring apparatus includes a framework having a pair of guide tracks and a carriage connected to the framework for movement along the tracks. The apparatus includes a mechanism for moving the carriage in forward or backward directions along the guide tracks. A drill assembly is mounted to the carriage having a drill motor for rotation of a drill rod releasably coupled thereto. A clamp assembly is mounted to one end of the framework and includes a clamp for selectively gripping the drill rod so as to rotatably release the drill rod from the drill motor when the drill motor is operated in a reverse direction. Upon release, the carriage may be moved to a start position, another drill rod may be attached to the drill motor and first rod, and boring resumed.

Underground horizontal boring apparatus

A system and method for a mixer circuit places the RF and mixer core LO transistors on the same level in anti-series. The mixer circuit provides increased headroom, excellent linearity, controllable conversion-gain, and operates with a reduced supply voltage requirement.

System and method for a mixer circuit with anti-series transistors

According to a broad aspect of the invention, an apparatus (34) for decoding a Manchester encoded data stream is provided. The apparatus includes a transition detector (45) for receiving the Manchester encoded data stream to produce a transition indicating output when a transition of the Manchester encoded data stream is detected. Also, a circuit (105) is provided to generate an output control pulse a predetermined time after the transition indicating output is produced. A sampling flip-flop (120) receives the Manchester encoded data stream, and is controlled by the output control pulse to output a state of the Manchester encoded data to an output control circuit (125) when the output control pulse is generated. In a preferred embodiment, the sampling flip-flop (125) operates to generate a binary NRZ form of the Manchester encoded data stream. The transition detector (45) may be configured to synchronize the transition indicating output with a pulse of a clock pulse stream, and also may include a phase selector to select either the first or second symbol of the Manchester data to the output of the apparatus.

Method and apparatus for decoding noisy, intermittent data, such as

A monolithic digital chirp synthesizer (DCS) chip using GaAs/AlGaAs HI.sup.2 L technology. The 6500 HBT gate DCS chip is capable of producing linear frequency modulated (chirp) waveforms or single frequency waveforms. The major components of the DCS are two pipelined accumulators, a sine ROM, a cosine ROM and two digital to analog converters.

Digital chirp synthesizer

A digital to analog converter and method for conversion is provided that includes an R-2R resistor ladder network formed with a plurality of current bit switches in a GaAs HI.sup.2 L integrated circuit. Each bit switch and R-2R node in the ladder network is associated with a corresponding bit position in the binary signal input to the converter. An arrangement of bipolar transistors (Q1, Q4) and diodes (D2-D3) is included in each bit switch (100) that steers current through one of two alternate paths, based on the logic state of the binary input signal (i e., 'high' or 'low' state). For one logic state of the binary input signal, current flows through the switch from the output of the digital to analog converter (110). For the alternate signal state, current flow from the output of the digital to analog converter is blocked. Therefore, each bit switch (100) operates as a single-pole-double-throw current mode switch under the control of the binary input signal (Ai). An arrangement of bipolar transistors (Q2, Q4) and a diode (D1 ) is also included to limit voltage swings and compensate for switching transients, which speeds up the recovery time of the switch and increases the overall switching speed of the digital to analog converter.

Method and apparatus for digital to analog conversion using GaAs HI.sup.2 L

A method and apparatus is provided for accurate digital to analog conversion in which bipolar voltage switches are used in a GaAs I.sup.2 L integrated circuit. An architecture is provided that includes an R-2R resistor ladder network formed in a GaAs I.sup.2 L integrated circuit. A compound transistor pair (Q1, Q2) is connected to each leg (2R) of the ladder network in a digital to analog converter (110). Each transistor pair (Q1, Q2) is configured as a single-pole-double-throw voltage bit switch (100). The transistor pair switches the shunt (2R) resistors between two, alternative voltage levels (Vb, circuit 'ground'), based on the state of the binary input logic signal (Ai). Each switch and respective leg in the ladder network relates to a corresponding bit position (Ai) in the input signal. A matched pair of diodes (D2, D3) are used to clamp the voltages to be selected by the bit switch (100) to a predetermined voltage level, thus regulating the voltages switched out to the ladder network and increasing the switching speed of the converter.

Method and apparatus for digital to analog conversion using gaas HI.sup.2 L

A digital to analog converter (10) and method is provided in which a plurality of digital to analog converter cells (16) generate an analog output signal based on a digital input signal, the cells being characterized by a switching threshold. An error signal circuit (22) generates a control voltage signal for controlling a first variable delay register (12). Signals latched by the first variable delay register (12) are characterized by rising and falling edges, and the first variable delay register (12) is controlled by the control voltage signal such that the rising and falling edges cross the switching threshold at substantially the same time.

Method and apparatus for digital to analog conversion with minimized

A caulking tool of flat, square-shaped plastic having each of its four corners rounded to form four different radii. The caulking tool is used after caulking material is applied to create a compacted, smooth, uniform bead. It is unique in its method of use and the choice of four different radii offering four choices of bead size from one tool.

Caulking tool

A semiconductor chip for processing or storing information and a system comprising a plurality of semiconductor chips for processing or storing information. In one form of the invention each chip includes clock input and output circuitry for receiving and transmitting signals of a first frequency and transmission circuitry for receiving and transmitting data. The transmission circuitry is capable of sampling the data at a second clock frequency which is less than the first clock frequency. Circuit components are coupled to the clock circuitry and transmission circuitry for processing the data. In another form of the invention a semiconductor chip comprising clock input and output circuitry, transmission circuitry and circuit components for processing data further includes input circuitry for selecting a variable delay between the time data is received onto the chip and transmitted from the chip In a preferred embodiment of the invention the semiconductor chip includes a memory array for storing data. The transmission circuitry includes a first path for transmitting received data to another like chip and a transmission path capable of combining data which is stored in the memory array with data which is stored in one or more like chips.

GaAs integrated circuit programmable delay line element

A digital memory system of the type which includes an amplifier transistor connected to provide an amplified bit line signal corresponding to the state of a selected memory cell. A bit line pull-up transistor is positioned to function as a bit line current source and as a load device for the amplifier transistor. The amplifier transistor is connected between the pull-up transistor and the bit line and an output node positioned between the pull-up and amplifier transistors provides the amplified bit line signal corresponding to the state of a selected memory cell.

Digital memory system

A MESFET logic gate wherein a logic switch node is both a-c coupled to the output node, preferably by a capacitor network and is also separately DC coupled to it, preferably by a voltage level shifter circuit. The direct capacitative coupling increases the high-frequency cut-off frequency, and reduces the current requirement of the voltage level shifter circuit. The voltage level shifter circuit, even using small width devices, provides low frequency and DC response, so that circuits using the gate of the present invention do not require initialization and refresh cycle. Thus, both high speed and low power are attained.

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Garland, TX, United States of America

William A White