Bull Hn Information Systems, Inc.

Honeywell Information Systems Inc.

Other

Honeywell Bull, Inc.

William A Shelly

Charles P Ryan

Russell Wayne Guenthner

Ronald E Lange

John E Wilhite

Marion G Porter

Clinton B Eckard

Minoru Inoshita

Ronald W Yoder

Robert J Baryla

Donald C Boothroyd

Wayne R Buzby

Garvin Wesley Patterson

David S Edwards

Leonard G Trubisky

Joseph Charles Circello

David A Egolf

Robert W Norman, Jr

Leonard Rabins

Earnest M Monahan

Lowell D McCulley

Ron Yoder

Jaime Calle

Bruce E Flocken

Richard L Demers

R Morse Wade

Bruce E Hayden

Eric Earl Conway

Boubaker Shaiek

Morgan S Riley

Kala J Marietta

Gary R Presley-Nelson

Claude Rabel

Jiuyih Chang

Elisabeth Vanhove

Stephen A Schuerich

Nicolas S Lemak

In a multiprocessor write-into-cache data processing system including: a memory; at least first and second shared caches; a system bus coupling the memory and the shared caches; at least one processor having a private cache coupled, respectively, to each shared cache; method and apparatus for preventing hogging of ownership of a gateword stored in the memory which governs access to common code/data shared by processes running in the processors by which a read copy of the gateword is obtained by a given processor by performing successive swap operations between the memory and the given processor's shared cache, and the given processor's shared cache and private cache. If the gateword is found to be OPEN, it is CLOSEd by the given processor, and successive swap operations are performed between the given processor's private cache and shared cache and shared cache and memory to write the gateword CLOSEd in memory such that the given processor obtains exclusive access to the governed common code/data. When the given processor completes use of the common code/data, it writes the gateword OPEN in its private cache, and successive swap operations are performed between the given processor's private cache and shared cache and shared cache and memory to write the gateword OPEN in memory.

Equal access to prevent gateword dominance in a multiprocessor write-into-cache environment

Cache memory, and thus computer system, reliability is increased by duplicating cache tag entries. Each cache tag has a primary entry and a duplicate entry. Then, when cache tags are associatively searched, both the primary and the duplicate entry are compared to the search value. At the same time, they are also parity checked and compared against each other. If a match is made on either the primary entry or the duplicate entry, and that entry does not have a parity error, a cache 'hit' is indicated. All single bit cache tag parity errors are detected and compensated for. Almost all multiple bit cache tag parity errors are detected.

High integrity cache directory

A plurality of processors in a data processing system share a common memory through which they communicate and share resources. When sharing resources, one processor needs to wait for another processor to modify a specified location in memory, such as unlocking a lock. Memory and bus traffic are minimized during this waiting by first reading and testing the memory location. Then, the memory location is not read and tested again until the local copy of the cache line containing that memory location is invalidated by another processor. This feature is utilized both for a Lock instruction and a Wait for Change instruction, both of which utilize a timer parameter for specifying a maximum number of cycles to wait for another processor to modify the specified location in memory.

Computer processor read/alter/rewrite optimization cache invalidate signals

A processor ( ) contains a Trace RAM ( ) for tracing internal processor signals and operands. A first trace mode separately traces microcode instruction execution and cache controller execution. Selectable groups of signals are traced from both the cache controller ( ) and the arithmetic (AX) processor ( ). A second trace mode selectively traces full operand words that result from microcode instruction ( ). Each microcode instruction word ( ) has a trace enable bit ( ) that when enabled causes the results of that microcode instruction ( ) to be recorded in the Trace RAM ( ).

Data processing system processor dynamic selection of internal signal tracing

In a NUMA architecture, processors in the same CPU module with a processor opening a spin gate tend to have preferential access to a spin gate in memory when attempting to close the spin gate. This &ldquo;unfair&rdquo; memory access to the desired spin gate can result in starvation of processors from other CPU modules. This problem is solved by &ldquo;balking&rdquo; or delaying a specified period of time before attempting to close a spin gate whenever either one of the processors in the same CPU module just opened the desired spin gate, or when a processor in another CPU module is spinning trying to close the spin gate. Each processor detects when it is spinning on a spin gate. It then transmits that information to the processors in other CPU modules, allowing them to balk when opening spin gates.

Gate close balking for fair gating in a nonuniform memory architecture data processing system

Gate close failure notification for fair gating in a nonuniform memory architecture data processing system

A processor ( ) in a data processing system simultaneously loads multiple registers ( ) with a single value for fast domain switching. A domain switch instruction asserts a register block write signal ( ) along with the register write signal ( ) when block writing the single value to the set of registers ( ). Register address lines ( ) are decoded in two sets: a first set of decoded address lines ( ) specifying a block of registers; and the second set ( ) specifying one register in the block of registers. When the register block write signal ( ) is asserted during a register write, the second set of decoded address lines ( ) are ignored, and all registers in the block of registers ( ) selected by the first set of decoded address lines ( ) are simultaneously loaded with a common value. Additional drive requirements are solved either by adding a buffer ( ) to each register bit, or by disabling ( ) the feedback path ( ) in each register bit during block writes.

Data processing system utilizing multiple resister loading for fast domain switching

Interactions among multiple processors (,) are exhaustively tested. A master processor (,) retrieves test information for a set of tests from a test table (,). It then enters a series of embedded loops, with one loop for each of the tested processors (,). A cycle delay count for each of the tested processors (,) is incremented (,) through a range specified in the test table entry. For each combination of cycle delay count loop indices, a single test is executed (,). In each such test (,), the master processor (,) sets up (,) each of the other processors (,) being tested. This setup (,) specifies the delay count and the code for that processor (,) to execute. When each processor (,) is setup (,), it waits (,) for a synchronize interrupt (,). When all processors (,) have been setup (,), the master processor (,) issues (,) the synchronize interrupt signal (,). Each processor (,) then starts traces (,) and delays (,) the specified number of cycles. After the delay, the processor (,) executes its test code (,).

Method and apparatus for exhaustively testing interactions among multiple processors

A processor (,) in a data processing system (,) provides a DELAY instruction. Executing the DELAY instruction causes the processor (,) to a specified integral number of clock (,) cycles before continuing. Delays are guaranteed to have a linear relationship with a constant slope with the specified number of clock cycles. Incrementing the specified delay through a range allows exhaustive testing of interactions among multiple processors.

Data processing system processor delay instruction

Two instructions are provided to synchronize multiple processors (,) in a data processing system (,). A Transmit Sync instruction (TSYNC) transmits a synchronize processor interrupt (,) to all of the active processors (,) in the system (,). Processors (,) wait for receipt of the synchronize signal (,) by executing a Wait for Sync (WSYNC) instruction. Each of the processors waiting for such a signal (,) is activated at the next clock cycle after receipt of the interrupt signal (,). An optional timeout value is provided to protect against hanging a waiting processor (,) that misses the interrupt (,). Whenever the WSYNC instruction is activated by receipt of the interrupt (,), a trace is started to trace a fixed number of events to an internal Trace Cache (,).

Apparatus for synchronizing multiple processors in a data processing system

Each processor (92) in a data processing system (80) caches a copy of the master calendar clock (97). The master calendar clock (97) and all of the cached calendar clocks (272) are periodically incremented utilizing a common clock (99). Whenever a processor (92) in the system (80) loads the master calendar clock (97) with a new value, that processor (92) broadcasts a cached calendar clock updated interrupt signal (276) to all of the processors in the system. In response to this interrupt (278), each processor (92) clears its cached calendar clock valid flag (274). Whenever a read calendar clock instruction is executed on a processor (92), the flag (274) is tested, and if set, its cached calendar clock (272) value is returned. Otherwise, the master calendar clock (97) value is retrieved, written to that processor's cached calendar clock (272), and returned. The cached calendar clock valid flag (274) is set to indicate a valid cached calendar clock (272).

Calendar clock caching in a multiprocessor data processing system

A computer system including a group of CPUs, each having a private cache which communicates with its CPU to receive requests for information blocks and for servicing such requests includes a CPU bus coupled to all the private caches and to a shared cache. Each private cache includes a cache memory and a cache controller including pairs of half-block operand buffers, each divided into quarter block segments. The operand buffer set is coupled to selectively receive, under control of an input multiplexer, requested information blocks from the CPU bus in quarter-block segments and is further coupled to selectively send, under control of an output multiplexer, received quarter-block segments to the CPU and received full blocks to the cache memory.

Information block transfer management in a multiprocessor computer

A computer system including a group of CPUs, each having a private cache which communicates with its CPU to receive requests for information blocks and for servicing such requests includes a CPU bus coupled to all the private caches and to a shared cache. Each private cache includes a cache memory and a cache controller having: a processor directory for storing identification words identifying information blocks resident in the cache memory and including a status field indicative of the write permission authority the local CPU has on the block, an output buffer for storing the identification words of a block resident in the cache memory for which the CPU does not have and seeks write permission and for selectively sending identification words and an invalidate command onto the CPU bus, an input buffer for storing the identification words of all recent write permission requests in the group, a comparator for comparing the identification words in the output buffer with the identifications in the input buffer and control logic, responsive to the comparator sensing a compare condition (typically indicating a request by another CPU for write permission on the same block for which the local CPU has also requested write permission), for aborting the write permission request of the local CPU and establishing a retry process.

Multiprocessor computer system incorporating method and apparatus for

A computer system including a group of CPUs, each having a private cache which communicates with its CPU to receive requests for information blocks and for servicing such requests includes a CPU bus coupled to all the private caches and to a shared cache. Each private cache includes a cache memory and a cache controller having: a processor directory for identifying information blocks resident in the cache memory, logic for identifying cache misses on requests from the CPU, a cache miss output buffer for storing the identifications of a missed block and a block to be moved out of cache memory to make room for the requested block and for selectively sending the identifications onto the CPU bus, a cache miss input buffer stack for storing the identifications of all recently missed blocks and blocks to be swapped from all the CPUs in the group, a comparator for comparing the identifications in the cache miss output buffer stack with the identifications in the cache miss input buffer stack and control logic, responsive to the first comparator sensing a compare (indicating a request by another CPU for the block being swapped), for inhibiting the broadcast of the swap requirement onto the CPU bus and converting the swap operation to a 'siphon' operation to service the request of the other CPU.

Private cache miss and access management in a multiprocessor system with

A fault tolerant computer system includes at least two central processing units each having a cache memory and a parity error detector adapted to sense parity errors in blocks of information read from and write to cache and to issue a cache parity read or write error flag if a parity error is sensed. A system bus couples the CPU to a System Control Unit having a parity error correction facility, and a memory bus couples the SCU to a main memory. An error recovery control feature distributed across the CPU, including a Service Processor and the operating system software, is responsive to the sensing of a read parity error flag in a sending CPU and a write parity error flag in a receiving CPU in conjunction with a siphon operation for transferring the faulting block from the sending CPU to main memory via the SCU (in which given faulting block is corrected) and for subsequently transferring the corrected memory block from main memory to the receiving CPU when a retry is instituted.

Fault tolerant multiprocessor computer system

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Phoenix, AZ, United States of America

William A Shelly