Digital Equipment Corporation

Hewlett-packard Development Company, L.p.

William A Samaras

Andrew D Ingraham

James B Keller

David J Sager

Robert E Stewart

Raj K Ramanujan

John DeRosa

David T Vaughan

Leon D Hesch

Robert T Silver

An apparatus comprises a plurality of ports wherein each port is adapted to couple to a device. At least one port connects by way of first and second unidirectional, point-to-point communication links with a device. The first unidirectional, point-to-point communication link transfers data from the device to the central logic unit and the second unidirectional, point-to-point communication link transfers data from the central logic unit to the device.

High speed bus system that incorporates uni-directional point-to-point buses

A high speed bus system for use in a shared memory system that allows for the high speed transmissions of commands and data between a number of processors and a memory array of a multi-processor, shared memory system, with the high speed bus system including a central unit and a series of uni-directional buses that connect between the plurality of processors and shared memory, with the central unit including arbitration logic and a series of multiplexers to determine which CPUs are granted access to shared buses, scheduling logic that works with the arbitration logic and multiplexers to determine which CPUs are granted access to the shared buses, and port logic for combining the CPU transmissions and determining if such transmissions are valid.

Data can be accurately transmitted between two subsystems in a synchronous system even if the clock skew or propagation delay between the two subsystems is greater than one clock cycle time. The source and destination subsystems are initialized to ensure synchronous operation. The source subsystem transmits data and a forwarded clock to the destination subsystem. The forwarded clock is passed through a delay device to introduce a one-half cycle delay into the forwarded clock timing. Data is captured in three state devices arranged in parallel to eliminate minimum delay requirements and to expand data valid time. The captured data is then aligned to the destination subsystem's clock by controlling a multiplexer which selects the proper signal at its input to pass to the input of a second state device coupled to its output. The data selected is then clocked into the second state device under the control of the distination subsystem's clock, thus aligning the received data with the destination subsystem's clock.

Method and apparatus for stabilized data transmission

A VSLI circuit includes a plurality of state device circuits on a VLSI chip. Each of the state device circuits includes a latch and is clocked by a pulse generator circuit which produces narrow pulses that are coupled to the clock input of the latch. The narrow pulses have a pulse width substantially equivalent to the propagation delay through the latch of the state device circuits. By taking advantage of the high correlative percentages of devices on portions of the chip, master-slave flip flops can be implemented using only a single latch with a pulse generator.

VSLI latch system and sliver pulse generator with high correlation factor

Data can be accurately transmitted between two subsystems even if the clock skew between the two subsystems is larger than one clock cycle by the method of the invention. In one embodiment data is loaded into N state devices in the sending subsystem while the receiver recovers data from the sending state devices in rotation with an N input multiplexer. Another embodiment forwards a clock signal from the sending subsystem along with a data vector of N state signals for recovery by a pair of state devices capturing data on the rising and falling edges of the forwarded clock. A further embodiment achieves double bandwidth by forwarding two clock signals.

A clock apparatus provides variable frequency system clock signals for synchronizing the operation of data processing apparatus and constant frequency timing signals, in phase with the system clock signals, for controlling the operation of an interval timer or related apparatus. The variable frequency system clock signals are produced by placing a controllable divider network in the phase locked loop. The input signals to the controllable divider network are distributed as the system clock signals. The constant frequency is obtained by distributing count signals from the controllable divider network of the phase locked loop circuit to a plurality of comparator circuits and output signals from the comparator provide a multiplicity of timing intervals that result in the constant frequency signals. The timing intervals are determined by the control signals that are applied to controllable divider network and to a plurality of divider circuits associated with the comparator circuits. The control signal is divided by the divider circuit and the resulting value entered in the comparator circuit where the value is compared with the count from the controllable divider network. A distribution network, used to provide a delay in the distribution of the system clock signals, thereby synchronizing components of the data processing system, is placed in the phase locked loop to insure that the signal to the constant frequency signals and the system clock signals are in phase.

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Haverhill, MA, United States of America

William A Samaras