At+t Corp.

Lattice Semiconductor Corporation

Other

Lucent Technologies Inc.

At&t Bell Laboratories

William A Oswald

Barry K Britton

Dwight D Hill

Eric Ting

Michael Lesile Roy

Wenyi Feng

Satwant Singh

Charles J Breidenstein

Klaus Gueldenpfennig

Stanley L Russell

Karam V Narula

A programming tool for programmable logic devices (PLDs), such as field programmable gate arrays (FPGAs), supports the display of hidden-switch connections, in addition to the display of conventional placed-switch, switch-box, and pseudo-arc connections. A hidden-switch connection between two functional elements in the PLD is represented in graphical displays generated by the programming tool as a curve (e.g., a diagonal straight line) from a jumper wire on the first functional element to another jumper wire on the second functional element, where a jumper wire is represented in the graphical display as a wire connected at one end to an pin of the corresponding functional element and unconnected at the other end. A programming tool that supports hidden-switch connections can be used to program FPGAs and other PLDs having architectures that were not previously supported by conventional programming tools that do not support hidden-switch connections.

Programming programmable logic devices using hidden switches

A field programmable gate array (FPGA) includes at least one programmable function unit (PFU) which comprises input lines, output lines, and a look-up table (LUT) for generating various functions in response to a configuration bit stream. A first function is an adder/subtracter in which the first input line provides an add/subtract control signal to a multiplexer coupled to a full-adder. The multiplexer determines whether a data bit or its complement is coupled to the full-adder. A second function is an AND gate coupled to the full-adder in which the first input line provides a data bit to the AND gate. The second function provides a basic cell for a parallel multiplier. Furthermore, the first input line may be used as a control line or a data line for a general logic function, depending on the PFU function.

Programmable function unit as parallel multiplier cell

Providing low-skew clock signals to a Field Programmable Gate Array (FPGA) chip normally requires devoting a certain number of bondpads to that purpose. However, that limits the number of clocks that may be applied, and may also limit which bondpads can be used for that purpose. In the present invention, any input/output bondpad may be used to supply a low-skew clock, or other global type signal, to one or more of the Programmable Function Units (PFUs). This is accomplished by using a criss-crossed grid of parallel conductor groups. Any of the conductors may be supplied by a clock from a bondpad or alternatively driven directly from a PFU, thereby allowing the distribution of internally-generated clocks. To facilitate programmable interconnects between the horizontal and vertical conductors, the outer conductor in a group crosses over the others at defined intervals, to thereby become the inner conductor. In this manner, each cell may drive a subset of the conductors in a group, thereby reducing the number of drivers needed. This allows all the buffer and conductor topologies to be identical for each cell, which significantly aids in the computer-aided design of the FPGA, as well as simplifying its programming.

Low-skew signal routing in a programmable array

A field programmable gate array (FPGA) includes a distributed switch matrix for programmably connecting the various routing conductors. The distributed switch matrix comprises groups of additional conductors, referred to as 'Switching R-nodes'. The Switching R-nodes programmably connect selected ones of the (e.g, horizontal) routing conductors to other selected ones of the (e.g., vertical) routing conductors. In this manner, the direct connection between the routing conductors may be avoided, allowing for a reduced number of programmable interconnect devices. In one preferred embodiment, a nibble-mode architecture is used, wherein four data conductors are provided for each group of routing conductors, with other multiples-of-four data conductors also being advantageous.

FPGA with distributed switch matrix

A field programmable gate array that includes a dedicated path that directly connects an I/O pad to a selected register in the array of programmable function units. For example, a direct connection (i.e., without a configurable interconnect point) is provided from an I/O pad, through an input driver, to the input of a selected register in a given PFU. Either this same path, or alternatively a different path, may be used to directly connect a register output from a given PFU to an I/O pad, through an output driver. This technique avoids the need for special I/O registers in the programmable input/output cells, thereby increasing the flexibility of use and ease of design of the FPGA.

Field programmable gate array with direct input/output connection

A digital private automatic branch exchange provides a plurality of ports which may comprise line trunks or operator circuits, the ports being grouped with each group being controlled by an individual microprocessor circuit which performs all real time control over the ports. Voice communication between ports is effected by time division multiplex in connection with a digital switch system forming part of a common control which is controlled by a central processing unit responsive to the microprocessors in each port group for assigning time slots to each interconnection channel. Isolation between the central processing unit and the rest of the system is provided by a peripheral bus to which the common control units and port groups are connected, which peripheral bus is connected to the CPU bus by way of an interface circuit, permitting the system to operate with various types of central processing units without redesign of the peripheral units. A conference circuit is also provided for making available a range of conference sizes by combining the available lines to the conference circuit into groups of a predetermined size which may be expanded by combining groups to form conferences of larger or intermediate size.

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Allentown, PA, United States of America

William A Oswald