Dell Products Inc.

Advanced Micro Devices Corporation

William A Moyes

Wei G Liu

Alexander J Branover

Kevin Michael Lepak

Wade Andrew Butcher

Anh Dinh Luong

Jonathan Foster Lewis

Juan Francisco Diaz

Philip John Brisky

Donald P Matthews, Jr

Michael V Mattress

A/D bit storage, processing, and mode management techniques through use of a dense A/D bit representation are described. In one example, a memory management unit employs an A/D bit representation generation module to generate the dense A/D bit representation. In an implementation, the A/D bit representation is stored adjacent to existing page table structures of the multilevel page table hierarchy. In another example, memory management unit supports use of modes as part of A/D bit storage.

A/D bit storage, processing, and modes

Systems, apparatuses, and methods for implementing a metadata tweak for channel encryption differentiation are disclosed. A memory controller retrieves a device-unique identifier (ID) from a memory device coupled to a given memory channel slot. The memory controller uses the device-unique ID to generate a tweak value used for encrypting data stored in the device. In one scenario, the device-unique ID is embedded in the address bits of the tweak process. In this way, the memory device can be migrated to a different memory channel since the data can be decrypted independently of the channel. This is possible since the device-unique ID used for the tweak operation is retrieved from the metadata stored locally on the memory device. In one implementation, the memory device is a persistent dual in-line memory module (DIMM). In some implementations, the link between memory controller and memory device is a compute express link (CXL) compliant link.

Metadata tweak for channel encryption differentiation

A system-on-chip with runtime global push to persistence includes a data processor having a cache, an external memory interface, and a microsequencer. The external memory interface is coupled to the cache and is adapted to be coupled to an external memory. The cache provides data to the external memory interface for storage in the external memory. The microsequencer is coupled to the data processor. In response to a trigger signal, the microsequencer causes the cache to flush the data by sending the data to the external memory interface for transmission to the external memory.

Enhanced durability for systems on chip (SOCs)

A method includes receiving reports of the pointing device events occurring on a remote computer at a host computer and performing computations in the host computer based upon the mouse reports. The method includes generating screen images in the host computer based upon the computations, the screen images not containing images of a cursor representing locations pointed to by a pointing device of the host computer. The generated screen images are transmitted to the remote computer. In some embodiments, the reports may be received by a remote console controller. An information handling system includes boot firmware to set a mouse to operate in absolute mode under control of the boot firmware. An information handling system separately transmits to a remote console controller of the information handling system screen images without a cursor and cursor images.

Synchronizing a cursor from a managed system with a cursor from a remote system

An information handling system includes a memory with a cache, and a processor to execute pre-operating system (pre-OS) code before the processor executes boot loader code. The pre-OS code sets up a Memory Type Range Register (MTRR) to define a first memory type for a memory region of the memory, sets up a page attribute table (PAT) with an entry to define a second memory type for the memory region, disables the PAT, and pass execution by the processor to the boot loader code. The first memory type specifies a first cacheability setting on the processor for data from the memory region, and the second memory type specifies a second cacheability setting on the processor for data from the memory region.

System and method for providing fine-grained memory cacheability during a pre-OS operating environment

An information handling system includes a processor; a memory, a firmware, and a video agent. The memory includes a frame buffer for image data. The frame buffer accessible to an operating system. The firmware is configured to present to the operating system a graphics output protocol. The graphics output protocol includes an address of the portion of the reserved portion of the memory and soft video display parameters. The video agent is configured to retrieve image data from the reserved portion of the memory, and provide the image data to an external system for remote video display to be completed upon finalization of application.

UEFI virtual video controller

In accordance with embodiments of the present disclosure, a device for persistent cached image download may include a memory, an input/output interface, and a network interface. The memory may be configured to store therein an image database, the image database comprising a boot image for each of one or more information handling systems. The input/output interface may be communicatively coupled to the memory and configured to couple to a corresponding input/output port of an information handling system. The network interface may be configured to couple to an image server. In response to an information handling system coupled to the input/output interface determining that the updated version of the particular boot image exists at the image server, the memory may store the updated version in the memory as the particular boot image.

Systems and methods for persistent cached image download

In a system having a plurality of processing nodes, wherein each of the plurality of processing nodes has an assigned portion of system memory such that the assigned portion of system memory of each of the plurality of processing nodes is accessible by the plurality of processing nodes, a technique is presented that allows each of the plurality of processing nodes to perform a memory initialization and test of the processing node's assigned portion of system memory. One of the processing nodes can cause the others of the processing nodes to perform the memory initialization and test process or each processing node can automatically perform the memory initialization and test process.

Growing community of inventors

Austin, TX, United States of America

William A Moyes