Storage Technology Corporation

Other

William A Burns

Stephen S Selkirk

Nicholas J Krull

Michael Lucas

Mark C Briel

James B Hall

Robert J Hancock

A high-bandwidth cache system serves computer elements such as processors and disk arrays through a serial interconnection architecture. The system includes a set of adapters, each adapter connected to at least one computer element, and a cache memory. The system also includes a set of bidirectional multichannel serial data links, each link connecting one of the adapters to the cache.

High bandwidth cache system

A system for busing data in a DASD controller is described. The system includes adapters serving computer elements such as processors and disk arrays. Cache memory in the controller is divided amongst memory cards. At least one switch is connected to each memory card. Bidirectional multichannel serial links connect each adapter with a switch. Each switch can establish at least one path between each adapter connected to the switch and each memory card.

High performance data paths

A plurality of transmitters are multiplexed to a hub through clocked serial links. Timing problems that may arise when switching between links are eliminated with a system including a group serial receiver for each link for performing serial to parallel conversion of data sent over the serial link, outputing a group clock signal based on the serial clock signal, outputing parallel data clocked by the group clock signal, and determining a data enable signal from the serial link. A select signal for determining the serial link being read by the hub selects the corresponding group clock, parallel data, and data enable. A load control clocks the selected parallel data into a first-in, first-out buffer using the selected group clock when the selected data enable is asserted. When the selected data enable is not asserted, the load control is held in reset and, hence, is insensitive to irregularities in the selected clock signal due to switching between links. Data is clocked from the buffer by a local clock.

System and method for multiplexing serial links

A direct access storage device (DASD) controller system for serves computer elements such as processors and disk arrays through a serial interconnect scheme. The system includes a plurality of adapters belonging to either a first set or a second set. Cache memory is divided into master memory cards and slave memory cards, each slave memory card in communication with a corresponding master memory card. A plurality of bidirectional multichannel serial data links connects one adapter with one memory card such that every adapter in the first set of adapters is connected to every master memory card and such that every adapter in the second set of adapters is connected to every slave memory card.

An improved rotary combustion engine is provided with a cylindrical intake and compression housing and a cylindrical combustion and exhaust housing. Each of the housings contain variable volume spaces defined by the inner surface of elliptically shaped openings in the housings, the outer surface of a rotor within the opening, fusiform shaped pistons and end walls perpendicular to the common axis of the cylinder and the rotor. The stages are coaxial and separated by a disk valve. The rotors within each housing are attached to the engine shaft. The pistons are supported in bearings mounted in end plates which are attached to the rotors. The attitude of the pistons is controlled during engine rotation by cams at each end of the engine. A mixture of fuel and air is drawn through one of two ports into variable volume spaces in the intake and compression housing by the relative motion of rotor and pistons. Further rotation seals the spaces and compresses the mixture. Continued engine rotation causes transfer of the compressed mixture into variable volume spaces in the combustion and exhaust housing where it is ignited. Ignition of the mixture forces the pistons in the combustion housing to orbit the engine shaft and rotational force is transmitted through end plates and the combustion rotor to the shaft. Continuing rotation of the engine forces exhaust gases to be expelled through two ports in the combustion and exhaust stage.

Rotary internal combustion engine

An error detection and correction method for digital data storage is described which comprises horizontal and vertical generation of parity check bits. These may be used to correct errors in up to two bits per word and to indicate whether all errors in a given record have been corrected during a read operation or not. Hamming codes are used to generate check bits in a vertical direction, while cyclic redundancy codes are used in the horizontal direction. The invention is described as embodied in a solid-state memory unit utilizing charge-coupled devices for data storage.

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Boulder, CO, United States of America

William A Burns