Emc Corporation

International Business Machines Corporation

Array Technology, LLC

Other

David W. Gordon

Walter a. Hubis

David C. Stallmo

David M. Warner

William a. Brant

William A Brant

Michael Edward Nielson

David C Stallmo

Gerald L Hohenstein

David W Gordon

Richard D Carmichael

Gary Neben

Tin S Tang

Randy Hall

Noel Simen Otterness

Joseph G Skazinski

Walter A Hubis

Thomas E Richardson

Edde Tin-Shek Tang

Gary Ward Howard

Mohamad H El-Batal

Mark S Walker

Albert S Lui

William G Deitz

Randall F Horning

Keith Edward Short

David M Warner

A process, apparatus, and system stores data check information on an electronic storage medium that uses standard sector data field sizes. The check information may include a cyclic redundancy check (CRC), a logical block address (LBA), a longitudinal redundancy check (LRC), state information, a sequence number, or other information to identify data state, misplacement, or corruption. The check information, instead of being appended to the data within the data sector, may be stored in an independent check sector. The check information corresponding to multiple data sectors may also be aggregated and stored in a single check sector. The process or apparatus may be incorporated in a storage system controller, a RAID controller, a software SCSI stack in a computer, an operating system, a storage device driver, or another appropriate application that interfaces with standard and commodity storage system components.

Process, apparatus, and system for storing data check information using standard sector data field sizes

A bridged controller for reducing the overhead of cache coherency processing on each of a plurality of primary controllers and increasing the overall throughput of the system. The bridged controller interfaces with dual-active pair of host-side controllers and the backend disk drive buses. The third controller allows a doubling of the number of backend busses, reduces the overhead of cache coherency processing on each primary host-side controller and doubles the overall throughput.

Apparatus for reducing the overhead of cache coherency processing on each primary controller and increasing the overall throughput of the system

A storage controller for redundant arrays of independent disks (RAID) comprises a daughter card containing a standardized controller core, which is mated to one of a number of customizable controller interface cards. The controller core card includes high performance elements such as a processor, cache memory, CRC circuitry, a host port, and a storage port. All operational communication with non-core components occurs via the host port and the storage port through the controller interface card. The controller core card monitors and configures communications between the host and the storage array. Each controller interface card is populated with components and connectors particular to the respective application or RAID system. The size and layout of the controller interface card may also be customized to the particular application. Sharing the same controller core card among various RAID controllers lowers the cost and time-to-market for customized RAID systems.

Modular RAID controller

Adaptive write policy for handling host write commands to write-back system drives in a dual active controller environment. Method for adaptive write policy in data storage system, where data storage system includes host system connected to primary controller and alternate controller. Controllers are coupled to system drive that includes one or more disk storage devices. Primary is connected to first memory and alternate is connected to second memory. Primary and alternate manage data storage system in dual-active configuration. Primary controller receives host write command from host system and write data request includes host write data. When system drive is configured with write-back policy, primary determines whether host write command encompasses an entire RAID stripe, and if so, primary processes host write command in accordance with write-through policy. Otherwise, primary processes command in accordance with write-back policy. Reduces amount of host write data that has to be mirrored to alternate controller.

System, apparatus and method providing adaptive write policy for disk array controllers

One embodiment of the present invention provides a procedure to configure the operation of the a device controller. In particular, the procedure operates in a system that includes a controller that is connected across a first input/output (I/O) interface to at least one other controlled device. An auxiliary computer is connected to the controller by a second I/O interface. The auxiliary computer has a processor therein for executing a set of computer program instructions stored in a first memory. The computer program instructions cause the auxiliary computer to first identify a set of resources in the system. Next, the auxiliary computer determines a set of compatible configuration options that are compatible with the identified resources. Next, the auxiliary computer generates an executable procedure from a number of software procedures that are stored in the memory of the auxiliary computer to implement the compatible configuration options. Finally, the auxiliary computer communicates the executable procedure into a second memory of the controller as controller configuration code.

System, apparatus, and method for configuring an array controller

This inventive provides a multiple level cache structure and multiple level caching method that distributes I/O processing loads including caching operations between processors to provide higher performance I/O processing, especially in a server environment. A method of achieving optimal data throughput by taking full advantage of multiple processing resources is disclosed. A method for managing the allocation of the data caches to optimize the host access time and parity generation is disclosed. A cache allocation for RAID stripes guaranteed to provide fast access times for the XOR engine by ensuring that all cache lines are allocated from the same cache level is disclosed. Allocation of cache lines for RAID levels which do not require parity generation and are allocated in such manner as to maximize utilization of the memory bandwidth is disclosed. Parity generation which is optimized for use of the processor least utilized at the time the cache lines are allocated, thereby providing for dynamic load balancing amongst the multiple processing resources, is disclosed. An inventive cache line descriptor for maintaining information about which cache data pool the cache line resides within, and an inventive cache line descriptor which includes enhancements to allow for movement of cache data from one cache level to another is disclosed. A cache line descriptor with enhancements for tracking the cache within which RAID stripe cache lines siblings reside is disclosed. System, apparatus, computer program product, and methods to support these aspects alone and in combination are also provided.

System, apparatus and method for multi-level cache in a multi-processor/multi-controller environment

A RAID-compatible data storage system which allows incremental increases in storage capacity at a cost that is proportional to the increase in capacity. The system does not require changes to the host system. The control and interface functions previously performed by a single (or redundant) central data storage device controller are distributed among a number of modular control units (MCUs). Each MCU is preferably physically coupled to a data storage device to form a basic, low-cost integrated storage node. One of two bus ports interfaces an MCU with the host computer on a host bus, and the other bus port interfaces an MCU with one or more data storage devices coupled to the MCU by a data storage device bus. The serial interface ports provide a means by which each of the MCUs may communicate with each other MCU to facilitate the implementation of a memory array architecture. The entire data storage array may appear as a single device capable of responding to a single identification number on the host bus, or may appear as a number of independent devices. A controlling MCU receives a command and notifies the other MCUs that are involved in a read or write operation. Control of the host bus is transferred from one MCU to the next MCU in sequence so that the data is received by the host computer, or written to each data storage device, in the proper order.

Distributed storage array system having plurality of storage devices which each of devices including a modular control unit for exchanging configuration information over a communication link

A fault-tolerant storage device array using a copyback cache storage unit for temporary storage. When a Write occurs to the RAID system, the data is immediately written to the first available location in the copyback cache storage unit. Upon completion of the Write to the copyback cache storage unit, the host CPU is immediately informed that the Write was successful. Thereafter, further storage unit accesses by the CPU can continue without waiting for an error-correction block update for the data just written. In a first embodiment of the invention, Read-Modify-Write operations are performed during idle time. In a second embodiment of the invention, normal Read-Modify-Write operation by the RAID system controller continue use Write data in the controller's buffer memory. In a third embodiment, at least two controllers, each associated with one copyback cache storage unit, copy Write data from controller buffers to the associated copyback cache storage unit. If a copyback cache storage unit fails, more than one controller share a single copyback storage unit. In a fourth embodiment, Write data is copied from a controller buffer to a reserved area of each storage unit comprising the array.

Storage device array architecture with copyback cache

A fault tolerant memory system is disclosed which includes a main memory device, storing data and an associated error detecting code, and a shadow memory device, storing data corresponding to the data stored in the main memory. A multiplexer, selectively couples data from either the main memory device or the shadow memory device to an output terminal in response to a control signal. A controller reads the data and associated error detecting code from the main memory device and the corresponding data from the shadow memory device, and generates the multiplexer control signal such that the multiplexer couples data from the shadow memory device to the output terminal if the data from the main memory device is not the same as the data from the shadow memory device and the error detecting code indicate an error in the data from the main memory device, and otherwise couples the data from the main memory device Lo the output terminal.

Fault tolerant memory system

Data is recovered despite a single point of failure in a data exchanging system while accommodating scaleable data transfer rate performance. In the environment of at least two disk array controllers, a serial dumping scheme assists in recovery of data from a fast memory. It is imperative to avoid loss of write data from a host computer which is received and acknowledged but not yet stored in a disk medium. The configuration ensures that at least one of the controllers will handle the data so as to correct single failure point errors and properly store that data on one of the disks of an array. A fast memory providing a buffer between a remote host computer and arrays of data storage media is managed so that data received for writing is duplicated for reliability of storage while data for reading to the host computer is manipulated with an enhanced bandwidth of fast memory operation.

Fault tolerant controller system and method

An address protection circuit (APC) for cross-checking the integrity of requests to read or write an addressable system memory in a fault-tolerant computer system. In a check mode, the APC checks each address and a source identification code of each memory access request from an address source. The source identification code and current bus address are compared to a range of addresses stored in the APC. If the current bus address is within an 'authorized' range, access to that range of locations in the memory is allowed to the address source. If a current memory access request is not authorized, the APC asserts an error signal which may be used to transfer control to a redundant subsystem. The APC contains a content-addressable memory element that can be initialized by a subsystem processor with address ranges and type of access (e.g., read or write) allowed for each source. To enter the setup mode, the APC must first be addressed to switch the APC from its check mode. Thereafter, only a single value in the APC can be changed by the processor. The APC then automatically reverts to its check mode. Further changes to values in the APC each require an explicit switch from the check mode to the setup mode.

Address protection circuit and method for preventing access to

A redundant array computer system having a high-speed CPU bus and lower-speed I/O buses, in which parity blocks are generated for a plurality of data blocks from multiple CPU bus logical channels in a randomly-interleaved manner to provide enhanced I/O transfer rates. For example, such a system may have two channels for processing two sets of data. The parity generation technique employs switching means to switch channels on the CPU bus between the first set and the second set, generating parity information that can be transferred independently over two I/O buses. The parity generation technique achieves an effective I/O bus transfer rate more closely matched to the speed of the CPU bus. The invention shares a single XOR gate and related support circuitry between multiple logical channels by providing a configurable electronic memory, thus achieving economies in implementation. For certain system applications, it may be desirable to utilize the RAM as a large, unified FIFO. Thus, the system can be adapted to generate parity information for very large blocks of data in a single channel.

Flexible parity generation circuit

Large numbers of relatively small (e.g., 1.8' or smaller) off-the-shelf disk drives are controlled to maximize the highest throughput performance at the least cost between a host computer and a mass storage subsystem. Host data is stored redundantly so as to form a cache. The controller recognizes data contained in its associated disk cache so as to produce that data to a requesting host with minimum delay. Data not in the disk cache as well as write commands are transferred to the controller of a mass storage subsystem with no substantial delay.

Disk based disk cache interfacing system and method

Data in a system having dynamic random access memories (DRAM's) is preserved despite loss of the primary source of electrical power to that system. A Flash RAM and a small auxiliary power source are employed by a controller independent of the system to transfer the DRAM contents to the Flash RAM immediately upon loss of primary system power. The data is also automatically returned to the DRAM after return of primary power with special data signals or sequences being utilized in a multiple controller environment so as to award the complete data recovery function to the first controller to demand attention.

Power failure responsive apparatus and method having a shadow dram, a

A RAID-compatible data storage system which allows incremental increases in storage capacity at a cost that is proportional to the increase in capacity. The system does not require changes to the host system. The control and interface functions previously performed by a single (or redundant) central data storage device controller are distributed among a number of modular control units (MCUs). Each MCU is preferably physically coupled to a data storage device to form a basic, low-cost integrated storage node. One of two bus ports interfaces an MCU with the host computer on a host bus, and the other bus port interfaces an MCU with one or more data storage devices coupled to the MCU by a data storage device bus. The serial interface ports provide a means by which each of the MCUs may communicate with each other MCU to facilitate the implementation of a memory array architecture. The entire data storage array may appear as a single device capable of responding to a single identification number on the host bus, or may appear as a number of independent device. A controlling MCU receives a command and notifies the other MCUs that are involved in a read or write operation. Control of the host bus is transferred from one MCU to the next MCU in sequence so that the data is received by the host computer, or written to each data storage device, in the proper order.

Growing community of inventors

Boulder, CO, United States of America

William A Brant