U.S. Philips Corporation

Willem Van Der Wel

Ronald Koster

Alexander C Jansen

Armand Pruijmboom

Godefridus A Hurkx

Catharina H Emons

A method of manufacturing a semiconductor device with a bipolar transistor (1) and a MOS transistor (2) formed in a silicon body (3) which for this purpose is provided with a field insulation region (4) by which semiconductor regions (6, 7) adjoining a surface (5) of said body are mutually insulated. A first region (6) is destined for the bipolar transistor and a second region (7) for the MOS transistor. The second region is provided with a gate dielectric (10). Then an electrode layer of non-crystalline silicon (11) is provided on the surface, which electrode layer is provided with a doping and in which electrode layer subsequently an emitter electrode (12) is formed on the first region and a gate electrode (13) on the second region. The electrode layer is provided with a doping by means of a treatment whereby a first dopant is provided at the area of the first region and a second dopant at the area of the second region, the first dopant being provided to a concentration such that the emitter zone of the transistor can be formed through diffusion from the emitter electrode to be formed in the electrode layer, while the second dopant is provided to a concentration lower than that of the first dopant. Owing to the comparatively low doping level, gate oxide breakdown is prevented during plasma etching and ion implantation.

Method of manufacturing a semiconductor device with a BiCMOS circuit

The continuing miniaturization of integrated circuits leads to a demand for ever higher resistance values. In conventional diffused resistors or poly resistors, an increase in the resistance value also means an increase in the surface area. Such resistors, moreover, are highly dependent on the doping concentration and sensitive to temperature changes. A resistor according to the invention comprises a resistor region 18 with a length and doping concentration which are chosen such that an electric field is applied at which velocity saturation of charge carriers takes place in the envisaged range of operation. The connection regions are connected to the resistor region via rectifying junctions 21, 22. In a specific embodiment, these junctions are formed by pn junctions, so that the resistor has, for example, an npn shape. The dimensions are furthermore chosen such that, within said operational range, electrons are injected into the p-type resistor regions by punch-through between the n-type connection regions 19, 20, traversing the resistor region at the saturation velocity. Since the charge carriers supplying the current are of the type opposed to that of the resistor material, it is prevented that the resistance value becomes very low at low voltages.

Punch-through resistor

A method of manufacturing a semiconductor device with a bipolar transistor (1) and a MOS transistor (2) formed in a silicon body (3) which for this purpose is provided with a field insulation region (4) by which semiconductor regions (6, 7) adjoining a surface (5) of said body are mutually insulated. A first region (6) is to be used for the bipolar transistor and a second region for the MOS transistor. The two regions are provided in that order with a gate dielectric layer (10) and an auxiliary layer (11) of non-crystalline silicon. The auxiliary layer and the gate dielectric layer are subsequently removed from the first region. Then an electrode layer (13) of non-crystalline silicon is deposited. An emitter electrode (15) is formed in the electrode layer on the first region, and a gate electrode (16) is formed both in the electrode layer and in the auxiliary layer on the second region. The electrode layer is subjected to a treatment whereby non-crystalline silicon is removed and whereby a layer of non-crystalline silicon is formed on the surface of the silicon body which has substantially the same thickness at the area of the first region and at the area of the second region. Overetching of the base zone (9) in the formation of the emitter is avoided thereby, so that the base zone may be comparatively thin.

Method of manufacturing a semiconductor device with BICMOS circuit

A method of manufacturing a semiconductor device whereby on a surface (3) of a semiconductor body (1) a conductor track (21) of polycrystalline silicon insulated from the surface (3) is provided in a layer of doped polycrystalline silicon (11) provided on a layer of insulating material (10), and whereby a strip of polycrystalline silicon (19, 35) is formed between an edge (18) of the conductor (21) and a portion (24, 34) of the surface (3) adjoining the edge (18), after which a semiconductor zone (30) is formed through diffusion of dopant from the conductor (21) through the strip (19, 35) into the semiconductor body (1). During the formation of the insulated conductor (21) and the strip of polycrystalline silicon (19, 35), a window (15) is etched into the layer of polycrystalline silicon (11) by means of a first etching mask (13), after which the insulating layer (10) is removed from the surface (3) within the window (15), the window (15) is provided at its edge (18) with a strip of polycrystalline silicon (19, 35), and the conductor (21) is etched into the layer of polycrystalline silicon (11) by means of a second etching mask (20), this second etching mask (20) covering at least a portion of the edge (18) of the window (15). Further conductors (22, 23) may be formed in the polycrystalline layer (11) next to the insulated conductor (21), all conductors (21, 22, 23) being given dimensions such as defined by the second etching mask (20).

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Nijmegen, Netherlands

Willem Van Der Wel