Teledyne Dalsa B.v.

National Semiconductor Corporation

Texas Instruments Corporation

Tetedyne Dalsa B.v.

Willem Johannes Kindt

Daniel Wilhelmus Elisabeth Verbugt

Michiel Antonius Petrus Pertijs

Athos Canclini

Sayyed Mahdi Kashmiri

Willem Johan De Haan

Chiel Smit

Hui-Yu Chen

Ernest Jannis Phaff

Bart Willem Jan Van Baarle

Alouisius W M Korthout

Daniël Wilhelmus Elisabeth Verbugt

Alouisius WM Korthout

An energy-resolving photon counting detector pixel. The energy-resolving photon counting detector may include a plurality of such pixels. In an embodiment, the detector pixel is operable in a calibration mode, in which mode an offset unit determines a correction signal to be provided to the detecting unit and/or to the comparing unit for correcting an offset in the detecting unit and/or comparing unit.

Energy-resolving photon counting detector pixel

Aspects of the present disclosure relate to an energy-resolving photon counting detector pixel. Further aspects of the present disclosure relate to an energy-resolving photon counting detector comprising a plurality of such pixels, and to an energy-resolving photon counting system comprising the same. In accordance with an aspect of the present disclosure, a CSA base level shift detector is used for determining a shift in the CSA base level over time relative to a first level. The pixel is configured to reset the CSA in dependence of the determined CSA base level shift.

Aspects of the present disclosure relate to a photon counting detector and to a read-out integrated circuit to be used in such detector. Aspects of the present disclosure particularly relate to X-ray applications. According to an aspect of the present disclosure, the detector comprises an electrical ground plane arranged at or near an interface between the carrier and at least one ROIC die. Each ROIC die comprises an extension region that laterally extends beyond the photon conversion assembly, wherein peripheral circuitry for a given ROIC die is arranged in the extension region of that ROIC die. The detector comprises at least one electrical connection that connects the power supply line that is arranged on the carrier to the peripheral circuitry of the at least one ROIC die.

Photon counting detector

The present invention relates to a fault detection circuit for detecting one or more column faults in a pixel array of an image sensor. The present invention further relates to a readout circuit for reading out a column line of an image sensor, and to an image sensor comprising the same. The fault detection circuit according to the invention comprises a signal unit for applying an electrical signal to a given column line of the pixel array, a determining unit for measuring a response to the applied electrical signal and for determining whether a fault exists for said given column line in dependence of the measured response, and a controller for controlling the signal unit and the determining unit, and for outputting a fault status for said given column line.

Fault detection circuit for image sensor

The present invention relates to an image sensor and to an imaging system comprising the same. The present invention particularly relates to X-ray image sensors and imaging systems. The image sensor according to the invention comprises a pixel array that includes a plurality of active pixels arranged in a matrix of rows and columns, and a plurality of column lines to which outputs of pixels in the same column are coupled for the purpose of outputting pixel signals. The image sensor further comprises readout circuitry that includes a plurality of readout units, each readout unit being configured for reading out a respective column line through an input node of the readout unit. The image sensor is characterized in that the image sensor further comprises capacitive units, such as capacitors, for capacitively coupling each input node to its corresponding column line.

Image sensor and imaging system comprising the same

A fluxgate sensor including a magnetic-to-digital converter (MDC) can be adapted to measure an external magnetic field Bwith a bandwidth f. The MDC forward path can include: (a) converting an analog sense signal from the fluxgate sense coil to corresponding oversampled digital data using an oversampling data converter with an oversampling frequency fgreater than f; and (b) loop filtering the oversampled digital data, synchronous with the oversampling frequency f, to generate the loop output digital data. The MDC feedback path can include: (a) generating the feedback compensation current Ifrom the loop output digital data, synchronous with a feedback path frequency fequal to ((M/N)&#xd7;f), where, M and N are integers; and (b) injecting the feedback compensation current Iinto the fluxgate compensation coil to induce the compensation field B, such that the induced compensation field Bnulls the external field B.

Fluxgate magnetic-to-digital converter with oversampling closed loop

An apparatus includes a sense module configured to be coupled to at least one power supply, where the sense module has a first leg. The apparatus also includes a replica module having a second leg, where the first and second legs have a common structure. The apparatus further includes a feedback loop configured to cause an output voltage across terminals of the replica module to at least substantially equal an input voltage across terminals of the sense module based on sense currents in the first and second legs. At least one cascode stage coupled to the sense module can be configured to reduce a voltage at which one or more signals from the sense module are referenced. One or more trim units can be used to reduce a gain error and/or an offset error between the input voltage and the output voltage.

Stacked power supply monitor with sense-replica loop

A circuit includes an input stage configured to receive and amplify an input signal to produce an amplified signal, where the input signal is referenced to a higher voltage and is associated with a common mode voltage. The circuit also includes level shifter resistors configured to level shift the amplified signal to produce a shifted signal. The level shifter resistors are configured to provide a voltage drop so that the shifted signal is referenced to a lower voltage. The input stage may include multiple transistors floating in one or more isolated portions of a substrate, where the transistors perform amplification in the input stage. The circuit may also include circuitry configured to control current through the level shifter resistors so that the voltage drop depends on the common mode voltage of the input signal. In addition, the lower voltage may be between supply rails of the circuit.

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Berkel en Rodenrijs, Netherlands

Willem Johannes Kindt