National Semiconductor Corporation

Eastman-kodak Company

Willem J Kindt

Christina P Phan

Brian D Segerstedt

Peter J Hopper

Vladislav Vashchenko

Philipp Lindorfer

Bumha Lee

Rudolphe Gustave Hubertus Eschauzier

Arie J Van Rhijn

Shivani Gupta

Alex Chung-Chun Lin

Gertjan V Sprakelaar

In a high voltage ESD protection solution, a plurality of DIACs are connected together to define a cascaded structure with isolation regions provided to prevent n-well and p-well punch through. An p-ring surrounds the DIACs and provides a ground for the substrate in which the DIACs are formed.

Cascoded bi-directional high voltage ESD protection structure

A method and apparatus for handling bad pixels in an image sensor array includes processing data values associated with the pixels of the image sensor. Processing the data values is performed by at least a first pass process and a subsequent pass process. In the first pass, the data values associated with the pixels are analyzed to determine whether any of the pixels are bad pixels. Information identifying the bad pixels is stored in a memory storage area of limited size. The stored information may also include an indicator, indicating a confidence level in categorizing the bad pixel. During the first pass, an overflow mark is stored in the memory storage area when insufficient memory storage is available for storing the information about a particular bad pixel. The overflow mark identifies the particular pixel in the image sensor array. During subsequent passes, processing may be redirected to the first pass to resume first pass processing of the data value associated with the particular pixel identified by the overflow mark. Based on information stored in the memory storage area, subsequent passes determine which data values are re-evaluated and whether the categorization of any particular bad pixel may be modified based on the re-evaluation. Corrected data values for each bad pixel may be determined by interpolating data values associated with neighboring pixels to each bad pixel. The first pass may be performed in response to a reset signal and the subsequent pass may be performed at a pre-determined time interval or event.

System and method for handling bad pixels in image sensors

A constant-transconductance rail-to-rail CMOS input circuit with offset trim is provided. PMOS and NMOS differential trim stages are scaled versions of PMOS and NMOS input stages respectively. The differential trim stages are configured to adjust the offset of the differential output current with accuracy over temperature. A first current mirror circuit is configured to receive a fraction of a bias current (&#x3b2;I), where &#x3b2; is related to the input common mode voltage. A second current mirror circuit is configured to receive another fraction of the bias current ((1&#x2212;&#x3b2;)I). The first current mirror circuit is configured to provide current &#x3b2;I to the PMOS input stage, and a scaled-down version of current &#x3b2;I to the PMOS differential trim stage. The second current mirror circuit is configured to provide current ((1&#x2212;&#x3b2;)I) to the NMOS input stage, and a scaled-down version of current ((1&#x2212;&#x3b2;)I) to the differential PMOS trim stage.

Offset trim circuit and method for a constant-transconductance rail-to-rail CMOS input circuit

An automatic exposure system is arranged to dynamically adjust the exposure time and gain of a pixel array in an imaging system. A selected group of pixels from the pixel array are evaluated while the pixel array is exposed to light that is reflected from a scene. The signal levels associated with the selected pixels are compared to a dynamically adjusted exposure threshold level, while the current exposure time is compared to a dynamic adjusted exposure time limit. The exposure threshold level and exposure time limit are selected using a method that is optimized for lower noise and less blur in the resulting image. The optimization method includes an optimal exposure method, an extrapolative method, an iterative method, and an alternative iterative method. The optimization methods are arranged to find an optimum balance between exposure time and gain such that noise and motion blur are minimized in the resulting image.

Automatically balanced exposure time and gain in an image sensor

An automatic exposure system is arranged to dynamically adjust the exposure time of a pixel array in an imaging system. A selected group of pixels from the pixel array are evaluated using a non-destructive readout procedure to determine the proper exposure time for the pixel array, while the pixel array is exposed to light that is reflected from a scene. Threshold detectors are employed to compare the signals from the selected group of pixels to a peak level that corresponds to a threshold limit for the pixels. The exposure of the pixel array is terminated when at least one pixel from the selected group of pixels exceeds the threshold limit. The threshold limit may be set to a level that is below total saturation for the pixels such that an overexposure margin is provided. Enhanced image contrast is achieved using automatic exposure time adjustment.

Automatic exposure control for an image sensor

An input stage employs low-voltage MOSFETs as input devices for an operational amplifier circuit that operates at common mode voltages that may exceed the gate-oxide breakdown voltage of the input devices. Also, the input stage is arranged for relatively low noise. The input stage is arranged to detect the input common mode voltage and to feed back the detected input common mode voltage to a base of a bipolar folded cascode transistor that is coupled to the drain of the input devices. Accordingly, the input devices are bootstrapped such that they are protected from gate-oxide breakdown.

Apparatus and method for receiving high-common mode voltage range signals with low-voltage devices

A circuit and method for increasing the dynamic range of CMOS image sensors designed with a thin gate oxide layer. The circuit includes a high voltage supply circuit and a high voltage level shifter circuit. The high voltage supply circuit is configured to supply a voltage to the shifter circuit. The voltage has a voltage level higher than the maximum supply voltage of the associated fabrication process. The shifter circuit is configured to output a high reset signal based on a reset signal generated to reset a pixel circuit of a pixel array. Instead of the reset signal, the high reset signal is coupled to a gate of the reset transistor in the pixel circuit. The high reset signal allows the reset transistor to maintain a gate to source potential less than the maximum supply voltage even when the high reset signal is greater than the maximum supply voltage.

High voltage reset method for increasing the dynamic range of a CMOS image sensor

A differential voltage amplifier includes a dynamic level shifter circuit and an amplifier circuit. The dynamic level shifter circuit includes high-impedance current sources and resistors that are arranged to move the common-mode levels of a differential input signal to a signal level that is suitable for the amplifier circuit. The amplifier circuit may be single-ended or differential. The dynamic level shifter circuit may include one or more current sources that are arranged to provide improved performance for low common-mode levels. A dynamic biasing scheme may be employed to improve operation over varied common-mode ranges. A trimming circuit may be used to adjust offsets in the system. A DC chop arrangement may be employed to remove offsets in the system.

Apparatus for sensing differential voltages with high common-mode levels

An improved vertical photo-detector cell is used in an imaging sensor. Sensor material associated with a given color in a vertical photo-detector cell is coupled to sensor material associated with the same color in an adjacent photo-detector cell such that photo-carriers from adjacent cells are combined. The coupled sensor materials result in an increased size sensor area for the given color. The increased sensor area associated with each pixel in the sensor results in increased sensitivity and improved fill factor for each color. In an imaging sensor array, the vertical photo-detector cells are arranged such that each color plane is arranged in a pattern. Each sensor in a pattern has a central portion and an extending portion. The central portion and the extending portion are each located about a geometrical center that is associated with a pixel in the array.

Vertical color photo-detector with increased sensitivity and compatible video interface

The present invention is directed to a photogate based pixel cell with an electronic shutter and which provides relatively low lag and high sensitivity for sensing infrared light reflected from objects. Additionally, this invention eliminates the need for a transfer gate in the pixel cell. In one embodiment, the reset and shutter transistors are implemented with PMOS transistors so that the pixel cell can have an increased dynamic range and a relatively high voltage swing. In another embodiment, the actual size of each pixel cell can be further reduced when the reset gate and the electronic shutter are implemented with NMOS transistors. Also, when a P&minus; well is not disposed beneath the photogate, the ability of the pixel cell to sense infrared light is improved. Correlated double sampling can be used to improve the accuracy of the signal read out from the pixel cell.

Apparatus for high sensitivity, low lag, high voltage swing in a pixel cell with an electronic shutter

An image sensor is disclosed that contains pixel cells that can individually provide a real-time output signal that is proportional to the instantaneous magnitude of incident radiation upon each pixel cell. The individual real-time output signals can be used to construct an electronic image. Additionally, the pixel cells of the image sensor can be used to collectively provide an accumulated real-time output signal that is proportional to the instantaneous magnitude of incident radiation upon a plurality of selected pixel cells. A propagated signal from a source such as a laser can be used to illuminate a target in an image. A reflection from the target can be detected in the accumulated real-time output signal. The range to the target can be determined using the round-trip propagation time between the sensor and the target of a propagated signal.

Integrated range finder and imager

An image sensing pixel cell includes a reset circuit, a capacitance, a photodiode, an amplifier circuit, and a voltage buffer. The reset circuit couples an initial voltage to a first node at an initial time, where the capacitance stores the initial voltage. The amplifier circuit is arranged to bias the photodiode at a relatively constant voltage. The voltage buffer circuit buffers the first node to produce a second voltage that corresponds to the voltage at the first node at a subsequent time. The second voltage is different from the initial voltage when a photocurrent flows in the photodiode. A pixel cell may include a shutter circuit having a closed position and an open position. The shutter circuit provides a conductive path for the photocurrent between the photodiode and a power supply connection when in the closed position. The shutter circuit provides another conductive path for the photocurrent between the photodiode and the first node when in the open position. In operation, every pixel cell in the array is reset at substantially the same time. The shutter opens for the entire pixel array to allow photocurrents to integrate on the capacitors in each pixel cell. The shutter closes and image data is read from the array of pixel cells. The image data for an image corresponds to the integrated photocurrents stored on the capacitors in the array of pixel cells.

Method and apparatus for a pixel cell architecture having high sensitivity, low lag and electronic shutter

A method and apparatus are provided for adjusting an offset in an electronic circuit by shifting at least one threshold voltage of a MOS transistor in an electronic circuit. By biasing a transistor into hard saturation, with sufficient supply voltage, charge carriers will be injected into the oxide layer of the MOS transistor over a predetermined time interval. Injection of charge carriers into the oxide layer of a MOS transistor causes the absolute value of the MOS transistor threshold voltage to increase. The injection of charge carriers is used to either intentionally increase or decrease the offset voltage in an electronic circuit due to mismatched components, process variations or to improve overall system accuracy or performance. In an operational amplifier or comparator, systematic offset voltage is measured at the output of the amplifier, and the threshold voltages of the differential input stage transistors are adjusted accordingly. In a digital to analog converter using precision current sources, the output voltage is measured for various code bits and the current levels for each current source are adjusted by shifting the threshold voltages as required. Offset voltage or mismatches in currents may be shifted in packaged electronic parts. The hot carrier injection method and apparatus, does not alter the temperature coefficient of the electronic part, requires minimal additional circuitry in electronic circuits, and greatly improves the precision with which electronic circuits may be manufactured.

Offset trim using hot-electron induced VT-shifts

An active pixel sensor cell array including a XDR reset signal generation circuit configured to generate XDR reset signals having user-selected levels, and an XDR reset signal generation circuit for use with such an array. The XDR reset signal generation circuit includes a digital-to-analog converter (DAC) coupled to receive control bits which determine the level and time of assertion of each XDR reset signal, and a level shifting circuit coupled to the output of the DAC. In response to the control bits (typically a sequence of multi-bit words), the circuit asserts a time-varying XDR reset potential. The XDR reset potential's amplitude as function of time (during each integration period) determines the breakpoints of each cell's response curve. The level shifting circuit includes a reference transistor, whose current density matches that of the reset transistors inside the cells, which shifts the potential at the DAC's output upward by an amount equal to the reference transistor's threshold voltage (which matches the threshold voltage of each reset transistor of the cell array or a row of the cell array) to produce the XDR reset potential. To cause the control bits asserted to the DAC to establish breakpoints which in turn cause the analog-to-digital converter (ADC) of the image sensor array to assert (predictably) an expected set of digital output bits in response to each read of a cell exposed to light of known intensity, both the ADC and the DAC operate at the same reference voltage, and the level shifting circuit's reference transistor's biasing matches that of the reset transistors inside the cells.

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Santa Clara, CA, United States of America

Willem J Kindt