General Instrument Corporation

Rca Inc.

General Semiconductor, Inc.

Other

General Instrument Corporation of Delaware

Willem G Einthoven

Jack Eng

Muni M Mitchell

Lawrence LaTerza

Dennis Garbis

Joseph Y Chan

Gregory Zakaluk

John Amato

Gary Horsman

Linda J Down

Jun Wu

Aidan Walsh

Danny Garbis

Anthony Ginty

William Hulstrunk

Richard Denning

Robert L Fried

Albert Alexander Todd

Sandy Tan

John E Amato

William Cordt Simpson

Anthony Joseph Caravaggio

Lou Schilling

Lawrence c/o General Semiconductor Inc Laterza

Danny c/o General Semiconductor Inc Garbis

A method of making a bi-directional transient voltage suppression device is provided, which comprises: (a) providing a p-type semiconductor substrate; (b) epitaxially depositing a lower semiconductor layer of p-type conductivity; (c) epitaxially depositing a middle semiconductor layer of n-type conductivity over the lower layer; (d) epitaxially depositing an upper semiconductor layer of p-type conductivity over the middle layer; (e) heating the substrate, the lower epitaxial layer, the middle epitaxial layer and the upper epitaxial layer; (f) etching a mesa trench that extends through the upper layer, through the middle layer and through at least a portion of the lower layer, such that the mesa trench defines an active area for the device; and (g) thermally growing an oxide layer on at least those portions of the walls of the mesa trench that correspond to the upper and lower junctions of the device.

Low-voltage punch-through bi-directional transient-voltage suppression devices having surface breakdown protection and methods of making the same

A bi-directional transient voltage suppression device with symmetric current-voltage characteristics has a lower semiconductor layer of first conductivity type, an upper semiconductor layer of first conductivity type, and a middle semiconductor layer adjacent to and disposed between the lower and upper layers having a second opposite conductivity type, such that upper and lower p&minus;n junctions are formed. The middle layer has a net doping concentration that is highest at a midpoint between the junctions. Furthermore, the doping profile along a line normal to the lower, middle and upper layers is such that, within the middle layer the doping profile on one side of a centerplane of the middle layer mirrors the doping profile on an opposite side. In addition, an integral of the net doping concentration of the middle layer taken over the distance between the junctions is such that breakdown, when it occurs, is punch through breakdown, rather than avalanche breakdown.

Low-voltage punch-through bi-directional transient-voltage suppression devices and methods of making the same

A bi-directional transient voltage suppression device is provided. The device comprises: (a) a lower semiconductor layer of p-type conductivity; (b) an upper semiconductor layer of p-type conductivity; (c) a middle semiconductor layer of n-type conductivity adjacent to and disposed between the lower and upper layers such that lower and upper p-n junctions are formed; (d) a mesa trench extending through the upper layer, through the middle layer and through at least a portion of the lower layer, such that the mesa trench defines an active area for the device; and (e) an oxide layer covering at least portions of the walls of the mesa trench that correspond to the upper and lower junctions, such that the distance between the upper and lower junctions is increased at the walls. The integral of the net middle layer doping concentration of this device, when taken over the distance between the junctions, is such that breakdown, when it occurs, is punch through breakdown, rather than avalanche breakdown. A method of making such a device is also provided, which comprises: (a) providing a p-type semiconductor substrate; (b) epitaxially depositing a lower semiconductor layer of p-type conductivity; (c) epitaxially depositing a middle semiconductor layer of n-type conductivity over the lower layer; (d) epitaxially depositing an upper semiconductor layer of p-type conductivity over the middle layer; (e) heating the substrate, the lower epitaxial layer, the middle epitaxial layer and the upper epitaxial layer; (f) etching a mesa trench that extends through the upper layer, through the middle layer and through at least a portion of the lower layer, such that the mesa trench defines an active area for the device; and (g) thermally growing an oxide layer on at least those portions of the walls of the mesa trench that correspond to the upper and lower junctions of the device.

A bi-directional transient voltage suppression device with symmetric current-voltage characteristics has a lower semiconductor layer of first conductivity type, an upper semiconductor layer of first conductivity type, and a middle semiconductor layer adjacent to and disposed between the lower and upper layers having a second opposite conductivity type, such that upper and lower p-n junctions are formed. The middle layer has a net doping concentration that is highest at a midpoint between the junctions. Furthermore, the doping profile along a line normal to the lower, middle and upper layers is such that, within the middle layer the doping profile on one side of a centerplane of the middle layer mirrors the doping profile on an opposite side. In addition, an integral of the net doping concentration of the middle layer taken over the distance between the junctions is such that breakdown, when it occurs, is punch through breakdown, rather than avalanche breakdown.

Low-voltage punch-through bi-directional transient-voltage suppression devices

Starting with a semiconductor wafer of known type including an internal, planar p-n junction parallel to major surfaces of the wafer, one of the wafer surfaces is covered with a masking layer of silicon nitride. A plurality of intersecting grooves are then sawed through the masking layer for forming a plurality of mesas having sloped walls with each mesa including a portion of the planar p-n junction having edges which intersect and are exposed by the mesa walls. The groove walls and exposed junction edges are glass encapsulated in a process including heating the wafer. The masking layers are then removed in a selective etching process not requiring a patterned etchant mask, and the now exposed silicon surfaces at the top of the mesas, as well as the opposite surface of the wafer, are metal plated. The wafer is then diced along planes through the grooves for providing individual chips each having a glass passivated mesa thereon.

Semiconductor chips having a mesa structure provided by sawing

A semiconductor device comprises a monocrystalline silicon wafer having a major surface lying in the &lt;100&gt; crystal plane. Disposed on the surface is a mesa having a generally square cross-section with generally rounded corners. The mesa has four main side walls each having a slope of around 45 degrees with respect to the base plane of the mesa, and the horizontal edges of the main side walls are disposed at an angle of at least around 12 degrees to the &lt;110&gt; directions on the wafer surface. The corners of the mesa each comprises a number of surfaces also having slopes of around 45 degrees and one surface having a slope of around 54 degrees. A high-low (N.sup.+ N.sup.- or P.sup.+ P.sup.-) junction is disposed within the mesa and makes a continuous line intercept with the mesa side walls around the entire periphery of the mesa. Except for exceptionally small deviations of no great significance, the high low junction intercept is at a constant height location entirely around the mesa periphery. The mesa is formed by anisotropic etching using a mask having main sides disposed at an angle of at least around 12 degrees to the &lt;111&gt; directions and rounded corners.

Semiconductor device having a mesa structure for surface voltage

A high voltage silicon rectifier includes a substrate portion and an epitaxial mesa portion that is a frustrum of a pyramid with a substantially square cross section and side walls that make a forty five degree angle with the substrate portion. The mesa portion includes three germanium doped layers that introduce strain to speed up recombination of charge carriers. The topography of the base region of the rectifier has a high-low junction that includes a central portion that is deeper in the mesa than the germanium-doped layers and an edge portion that is shallower in the mesa than the germanium-doped layers and forms a positive bevel angle with the tapered side walls of the mesa,

High voltage silicon diode with optimum placement of silicon-germanium

Significant reduction in the cost of fabrication of shallow junction, Schottky or similar semiconductor devices without sacrifice of functional characteristics, while at the same time achieving the advantages is achieved, after the non-polishing cleaning step is essentially performed, by subjecting the substrate to conditions which move disadvantageous factors within said substrate into a space substantially at said surface, followed by substantially removing said factor-containing space from said substrate chemical removal step, followed etching and vapor deposition steps. Although these new steps add time, and therefore cost, to the overall process, the devices under discussion when produced by known industry processes require yet more time, and involve yet more expense, so that the total process represents a substantial reduction in the cost of their manufacture while producing devices which are the equivalent or superior in electrical performance to such devices which are made by known industry processes.

Low cost method of fabricating shallow junction, Schottky semiconductor

Sets of six steering diodes and an ungated Thyristor are simultaneously formed into surge protection circuit modules by mass production techniques. An extended lead frame is provided with three spaced parallel leads for each module. The leads are connected at one end by a bridge. The sets of components are arranged along the lead frame in a fixture. By heating, each lead is soldered between a pair of steering diodes and the steering diodes on each side of the lead frame are soldered to different conductive plates. A thyristor is soldered between the plates. The partially formed modules are removed as a unit from the fixture and may be encased simultaneously. The bridge is removed to separate the modules and the leads trimmed and bent as required.

Surge protection circuit module and method for assembling same

A process for forming a semiconductor device begins by diffusing an N layer having a relatively high concentration into a P wafer having a relatively low concentration. Next, the wafer is etched to yield a plurality of mesa semiconductor structures, each having a P-N junction intersecting a sidewall of the mesa structure. Then, a layer of oxide is grown on the sidewalls of the mesas, which oxide layer passivates the device. The oxidizing step curves the P-N junction toward the P layer in the vicinity of the oxide layer. Then, the P-N junction is diffused deeper into the P layer with a diffusion front which tends to curve the P-N junction back toward the N layer in the vicinity of the oxide layer. This diffusion is carried out to such an extent as to compensate for the curvature caused by the oxidizing step and thereby substantially flatten the P-N junction. A plurality of successive oxidation/diffusion steps can be undertaken to further flatten the junction adjacent the mesa sidewall. The resultant P-N junction has a greater breakdown voltage in the vicinity of the oxide layer due to the substantial flatness of the P-N junction. The decreased concentration gradient of the linearly graded junction in the vicinity of the oxide layer caused by the oxidizing step increases the breakdown voltage in the vicinity of the oxide layer above the bulk breakdown voltage.

Passitvated mesa semiconductor and method for making same

A rectifier is fabricated from a P-N junction having a P-type semiconductor layer and an adjacent N-type semiconductor layer. A mesa structure is formed in at least one of said layers. Impurities are deposited at the top of the mesa to form a high concentration region in the surface thereof. The impurities are diffused from the top surface of the mesa toward the P-N junction, whereby the mesa geometry causes the diffusion to take on a generally concave shape as it penetrates into the mesa. The distance between the perimeter of the high concentration region and the wafer substrate is therefore greater than the distance between the central portion of said region and the wafer substrate, providing improved breakdown voltage characteristics and a lower surface field. Breakdown voltage can be measured during device fabrication and precisely controlled by additional diffusions to drive the high concentration region to the required depth.

Method for fabricating a rectifying semiconductor junction having

A process for forming a semiconductor device begins by diffusing an N layer having a relatively high concentration into a P wafer having a relatively low concentraton. Next, the wafer is etched to yield a plurality of mesa semiconductor structures, each having a P-N junction intersecting a sidewall of the mesa structure. Then, a layer of oxide is grown on the sidewalls of the mesas, which oxide layer passivates the device. The oxidizing step curves the P-N junction toward the P layer in the vicinity of the oxide layer. Then, the P-N junction is diffused deeper into the P layer with a diffusion front which tends to curve the P-N junction back toward the N layer in the vicinity of the oxide layer. This diffusion is carried out to such an extent as to compensate for the curvature caused by the oxidizing step and thereby substantially flatten the P-N junction. A plurality of successive oxidation/diffusion steps can be undertaken to further flatten the junction adjacent the mesa sidewall. The resultant P-N junction has a greater breakdown voltage in the vicinity of the oxide layer due to the substantial flatness of the P-N junction. The decreased concentration gradient of the linearly graded junction in the vicinity of the oxide layer caused by the oxidizing step increases the breakdown voltage in the vicinity of the oxide layer above the bulk breakdown voltage.

Method of making a passivated P-N junction in mesa semiconductor

A wafer with a &lt;100&gt; orientation comprises N layer (middle layer) and a lightly doped P layer (top layer). A strongly doped N layer (source layer) is diffused into most of the top layer. An oxide layer is grown. A V groove with a flat bottom is anisotropically etched through openings in the oxide layer. The V groove is etched through the source layer and most of the P layer. The bottom of the groove initially is at a level above the junction between the top layer and the middle layer. Exposure to beam of phosphorus ions forms a shallow implanted channel region proximate the walls of the groove. An unwanted implanted region along the bottom of the groove is also formed. A second anisotropic etch, through the same oxide mask, deepens the groove bottom to a point below the junction, removing the unwanted portion of the implanted region along the groove bottom. The implanted concentration of the channel is later reduced as the gate oxide is formed. This method of groove formation can be used to set the threshold voltage of enhancement mode power MOSFETS, without compromising the breakdown voltage. It can also be used to produce depletion mode power MOSFETS with zero-gate on resistance values of a few MILLI-OHM CM.sup.2.

Method for setting the threshold voltage of a power mosfet

Rectifying P-N junction having improved breakdown voltage

A wafer with a &lt;100&gt; orientation comprises a strongly doped N layer (substrate), a lightly doped N layer (middle layer) and a lightly doped P layer (top layer). A strongly doped N layer (source layer) is diffused into most of the top layer. An oxide layer is grown. A V groove with a flat bottom is anisotropically etched through openings in the oxide layer. The V groove is etched through the source layer and most of the P layer. The bottom of the groove initially is at a level above the junction between the top layer and the middle layer. Exposure to beam of phosphorous ions forms a shallow implanted channel region proximate the walls of the groove. An unwanted implanted region along the bottom of the groove is also formed. A second anisotropic etch, through the same oxide mask, deepens the groove bottom to a point below the junction, removing the unwanted portion of the implanted region along the groove bottom. The implanted concentration of the channel is later reduced as the gate oxide is formed. This method of groove formation can be used to set the threshold voltage of enhancement mode power MOSFETS, without comprising the breakdown voltage. It can also be used to produce depletion mode power MOSFETS with zero-gate on resistance values of a few MILLI-OHM CM.sup.2.

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Belle Mead, NJ, United States of America

Willem G Einthoven