Mostek Corporation

Thomson Components-Mostek Corporation

Willard S Briggs

Isadore S Ferson

Alan D Gant

Isadore S Gerson

Parveen K Gupta

A microcomputer includes I/O ports and registers which are mapped in memory space along with RAM and ROM and in which hardware invisible to the programmer performs a bus arbitration sequence to acquire an external bus when an off-chip reference requires the bus; and in which memory space that is used for on-chip references is recovered for use in external memory by manipulating bits in the memory address.

Address-controlled automatic bus arbitration and address modification

A microcomputer architecture permits communication between a CPU and same-chip ports and input/output circuits to be carried only over a multiplexed address/data/interrupt bus, thereby permitting modified I/O hardware or other circuits to be included in the microcomputer without disturbing the CPU layout.

Single-chip microcomputer with internal time-multiplexed

A set of clock-controlled CMOS logic circuits employ a single pair of non-overlapping clocks controlling a set of transmission gates that have only a single pass transistor and a compensating non-standard threshold voltage in a portion of the logic gates.

Non-overlapping clock CMOS circuit with two threshold voltages

An integrated-circuit CPU saves layout space by employing the Address Register as the Extension Register for multiplication operations, the Address Register being modified to include shifting hardware.

Multiplier with hybrid register

A microcomputer circuit is described for carrying out bit operations between registers and ports without the need for bit testing followed by branch operations. The microcomputer includes a bus (10) connected to provide communication to an ALU (22), registers (11, 12) and a serial port (13). A bit test circuit is connected to the bus (10) and provides a selected bit to a temporary carry storage (18) which in turn transfers the selected bit to a carry flag location (28a) within a status register (28). Instruction codes are input to an instruction register (32) which provides operating commands to an entry ROM (36) and an ALU control circuit (40). After a bit test operation is completed and in response to a copy or exchange instruction provided to the instruction register (32) a bit can be copied from one register to another register, bits can be exchanged between two registers or bits within a register can be parallel-to-serial converted and provided to the serial port (13). Each of these operations is carried out without the need for employing branch operations following the test of a bit. The present invention provides dynamic bit operations without the need for testing the state of a bit to determine conditional branching for selecting set or clear operations. With the present invention the speed of bit operations is improved and the amount of code stored in program memory can be reduced.

Growing community of inventors

Carrollton, TX, United States of America

Willard S Briggs