U.S. Philips Corporation

Wilhelmus J Josquin

Henderikus Lindeman

Henricus G Maas

Johannes A Appels

Jan Lohstroh

Jan Van Dijk

Alfred H Van Ommen

Albertus T Van De Goor

Wilhelmus C Peters

A method of manufacturing a semiconductor device is set forth, in which a conductive layer (21) and a first insulating layer (22) are provided on a surface (2) of a semiconductor body (1). A conductor track (5) with an insulating top layer (6) is formed in these layers and the top layer (6) is formed in a first insulating layer (22) by means of a first etching treatment. Further, while masking with the top layer (6), the conductor track (5) is formed in the conductive layer (21) by means of a second etching treatment, after which the conductor track (5) is provided with a side edge insulation (7). The surface (2) and the conductor track (5) with its top layer (6) are covered by a second insulating layer (24), which is then subjected to a third anisotropic etching treatment until this layer (24) has been removed from the surface (2) and the top layer (6). According to the invention, the second etching treatment is at least initially carried out so that the conductive layer (21) is etched isotropically, while the top layer (6) is then practically not attacked, cavities (31) are formed under the top layer (6) near its edges (30), after which the second insulating layer (24) is deposited in a thickness such that the cavities (31) are entirely filled with insulating material. Thus, the occurrence of leakage currents and shortcircuits between the conductor track (5) and the metallization (8; 9) to be provided on the insulation layers (6, 7) are avoided.

Method of manufacturing a semiconductor device, in which isolated

A semiconductor body (1) defines at least one active device. In the example shown in FIG. 1 complementary n channel and p channel IGFETs (10 and 20) are provided. An electrically conductive region, which may form the gate conductive region (101 and 102) of the insulated gates (11 and 21) of an IGFET, is provided on a first major surface (2) of the semiconductor body (1) and is encapsulated within a covering insulating region (300,400). An area (100a) of the electrically conductive region (101 and 102) contacts a relatively highly doped semiconductor region (50) provided adjacent the one major surface (2) and electrical contact is made to the electrically conductive region (101 and 102) via a conductive track (205) provided on the first major surface (2) and a conductive path provided by the relatively highly doped semiconductor region (50). It is thus not necessary to form a contact opening through the covering insulating region (300,400) to enable contact to the electrically conductive region (101 and 103) and accordingly electrical interconnections can overlap or cross over the encapsulated electrically conductive region (101 and 102).

Semiconductor device having an IGFET with diffused gate connection

A semiconductor body (1 ) is provided having a first region (4) of one conductivity type adjacent one major surface (2). An insulating layer (5) is formed on the one major surface and masking means (6,7) are used to form over first and second areas (20 and 21) of the one major surface (2) windows (8,9,10) in the insulating layer (5) through which impurities are introduced to form a relatively highly doped region (11) of the opposite conductivity type adjacent the first area (20) and a relatively lowly doped region (12) of the opposite conductivity type adjacent the second area (21). The surface (5a) of the insulating layer (5) is exposed prior to introducing impurities of the one conductivity type for forming a region (13) within the relatively lowly doped region (12) of the opposite conductivity type and with a dose sufficient to form the region (13) but not sufficient to overdope the relatively highly doped region (11) so avoiding the need to mask the first area (20) during this step. The thickness of the insulating layer (5) is such that a proportion of the impurities of the one conductivity type penetrate the insulating layer (5) to increase the doping of a surface layer(40) of the first region (4) so as to reduce problems such as punch-through effects.

Method of manufacturing a semiconductor device by maskless pn junction

A first device region (20) of one conductivity type is provided adjacent one major surface (11) of a semiconductor body (10). A layer (30) doped with impurities of the opposite conductivity type is provided on the one major surface (11) for forming an extrinsic subsidiary region (41) of a second device region (40) of the opposite conductivity type. An opening (31) is formed through the doped layer (30). Impurities for forming a coupling region (43) of the opposite conductivity type are introduced through the opening (31) prior to defining an insulating first portion (50) on the side wall (32) of the doped layer (30) to form a first window (80). Impurities for forming an intrinsic subsidiary region (42) of the second device region (40) are introduced through the first window (80). A second portion (60) is then defined on the insulating first portion (50) to form a smaller second window (90), and impurities for forming a third device region (70) through the second window (90) so that the extrinsic subsidiary region (41) and third device region are well spaced whilst the coupling region (43) enables good connection between the extrinsic and intrinsic subsidiary regions (41 and 42).

Method of manufacturing a bipolar transistor

A semiconductor device comprising a buried phosphor glass layer (5) consisting of a subjacent thick electrically insulating layer (4), a phosphor glass layer (6) and an overlying thin covering layer (7). According to the invention, the thicker electrically insulating layer (4) is locally removed and the combination of phosphor glass layer 6 and covering layer 7 is used as a dielectric for a capacitor. The invention also relates to a method of manufacturing a capacitor with indicated dielectric.

Method of making semiconductor device comprising a capacitor and a

The collector region (20) of a bipolar transistor (T) and a first well region (3) for an insulated gate field effect transistor (IGFET) (P) are formed of one conductivity type at respective first and second device areas (10 and 12) of a semiconductor body (1a). After definition of an insulated gate (9), opposite conductivity type impurities are introduced to form source and drain regions (90 and 91) of the IGFET (P) and at the same time to dope a dopable layer (30) on the first device area (10) to form an opposite conductivity type doped layer (30) for forming an extrinsic base region (40). An insulating layer (50, 51) is then provided to cover the first and second device areas (10 and 12). Impurities for forming an intrinsic base region (41) and emitter region (80) of the bipolar transistor (T) are introduced through an opening (60, 61) in the insulating layer (50, 51) which also serves to mask the IGFET (P) from these impurities.

Method of manufacturing a semiconductor Bi-CMOS device

Semiconductor device comprising a capacitor and a buried passivation

A method of manufacturing an integrated circuit is set forth comprising a field effect transistor having an insulated gate (35) and a further circuit element having a first (9) and a second electrode zone (14) of opposite conductivity types. Simultaneously with the gate (35) a conductive pattern (11) separated by an insulating layer (34) from the first electrode zone (9) is provided on the first electrode zone (9). This pattern (11) provides a pair of the edge of the doping opening (12) for the second electrode zone (14). A second insulating layer (16) is provided on the pattern (11) and is removed locally by anisotropic etching in such a manner that in the doping opening (12) edge portions (17) (16) are left. Subsequently, a conductive layer (22) for connection of the second electrode zone (14) is provided, which extends over the second insulating layer (16), over the pattern (11) and over the edge portions (17) (16 ) into the opening (12) of reduced size and on the second electrode zone (14). The contact opening for the second electrode zone (14) can thus be derved without alignment tolerance from the doping opening (12).

Method of manufacturing a semiconductor device

Two (polycrystalline) silicon tracks located at a relative distance of the order of submicrons which contact the subjacent semiconductor body with a pn junction formed therein, are connected to each other via a metal silicide track. The resulting shortcircuiting of the pn junction does not influence the operation of the circuit, for example, a memory cell, realized in the semiconductor body. By providing the whole conductor pattern with an oxide layer in which a contact hole is formed at the area of the shortcircuit, the latter can then be provided in a self-aligning manner.

Semiconductor device having silicon conductor tracks connected by a

In a LOCOS process, depressions are formed in a semiconductor body, and are filled by means of oxidation. The bottom and side walls of the depressions are coated with a double layer including an oxide and an oxidation-resistant material. This double layer is removed from the bottom of the depression and under-etching below the sidewalls under the oxidation-resistant layer is carried out to form cavities. As a result the remaining portions of the oxidation-resistant material are lifted along the surfaces of the side walls. With oblique walls for the depression, a high accuracy as to the size of active semiconductor regions can then be obtained with respect to an original mask.

In a method of manufacturing a semiconductor device, ions are implanted into a layer of silicon nitride over a part of its surface, and the layer is then subjected to an etching treatment. According to the present invention, before the etching treatment takes place, but after the ion implantation, the layer is subjected to a heat treatment in which the implanted part of the layer obtains a higher resistance to etching than the non-implanted part. The heat treatment occurs at temperatures above 750.degree. C. Thus, a negative image of a patterned ion irradiation can be formed in the silicon nitride layer. As a result, the number of cases in which an etching or oxidation mask can be formed in a silicon nitride layer without using additional mask is considerably increased.

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Eindhoven, Netherlands

Wilhelmus J Josquin