Blaupunkt-werke Gmbh

Robert Boschgmbh

Wilhelm Hegeler

Jurgen Kasser

Detlev Nyenhuis

Lothar Vogt

Harald Bochmann

Helmut Liman

Wolfgang Busse

Hans Rasehorn

Werner Henze

Lambert Maschmeyer

Peter Erben

The detection of short pulses of a digital input signal by an evaluation circuit, whose time intervals for polling the input signal are long compared to the duration of the pulses, is made possible by the formation of a difference between the input signal and an output signal formed from the input signal. A change in the output signal is effected proportionally to the difference with a large proportionality factor when the difference has a first operational sign, and proportionally to the difference with a small proportionality factor when the difference has another operational sign.

Method and circuit arrangement for detecting short pulses of a digital input signal

A process and apparatus for synchronizing the block counter of an RDS radio data receiver is described. According to the process, the bits stored in a 26-bit shift register, are cycled at least n times in said register, n being the number of allowable offset words, and the shift register content is X-OR gated with another offset word in a given sequence for each cycle. The gating result is received by a syndrome detection circuit, which triggers a sync pulse when the zero syndrome is detected, and the sync pulse resets the bit counter to zero and sets the block counter to the address counter status assigned to the offset word in the offset word generator.

Process and apparatus for synchronizing the block counter in an RDS radio data receiver

A device for synchronization of a block counter in an RDS receiver, the decoder of which, after synchronization has been effected, is capable of performing an error correction in the received bits. The process steps which can lead to synchronization of the block counter are integrated into the process steps for error correction, and are repeated in each bit period.

System for synchronizing a block counter in a radio-data-system (RDS) receiver

Process for providing a control, signal for controlling a radio receiver

Process for storing of data of a received carrier frequency of a

In a circuit for a demodulator of a radio data signal in a radio receiver, the multiplex signal in digital form is mixed into the baseband, in two phase positions shifted 90.degree. with respect to each other, after band-pass filtering, together with a reference carrier generated at a sampling clock rate produced in the radio receiver, thus producing a first and a second mix signal. A first and a second auxiliary signal with, respectively, a sine waveform and a cosine waveform are produced. The first mix signal is multiplied by the first auxiliary signal, and the second mix signal by the second auxiliary signal. The results of these multiplications are added together, producing a first output signal. The first mix signal is multiplied by the second auxiliary signal, and the second mix signal by the first auxiliary signal, and the results subtracted from each other, thus producing a second output signal. The phase position of the auxiliary signals is controlled in such a manner that the first output signal corresponds to the radio data signal (RDS) shifted down into the baseband.

Circuit for a demodulator for a radio data signal in a radio receiver

For a demodulator for radio data signals, where transmission of these signals is carried out through phase shifting of a suppressed subcarrier, where a multiplex signal, which contains a signal with the frequency of the subcarrier passes through a band-pass filter and an amplitude limiter, the amplitude-limited signal having a subcarrier frequency is transformed into digital sampling values, if necessary by additional filtering, and the sampling values are supplied to at least one phase control loop for deriving a bit clock signal.

Radio data signal demodulator with clock signal recovery

In a demodulator for use in the Radio Data System (RDS) as defined by the European Broadcasting Union, transmission of these signals is carried out through phase shift modulation of a suppressed subcarrier, a multiplex signal, which contains a signal with the frequency of the subcarrier passes through a band-pass filter and an amplitude limiter, and the amplitude-limited signal, having a carrier frequency, is sampled at a sampling frequency that is a multiple of the frequency of the subcarrier. The sampling values are summed over a preset portion of one period of the subcarrier. The summed sampling values are supplied to a digital signal processing circuit.

Demodulator for radio data signals

The Radio Data System (RDS) protocol promulgated by the European Broadcasting Union provides for alternate frequencies (AF) for the same broadcast. Receivers periodically switch over to such an alternate frequency, leading to momentary crackling noises. In a radio receiver having a device for temporary switchover from a received frequency to some other frequency, substitute signals are inserted into the audio signals that are interrupted during the temporary switchover. The substitute signals are formed from the audio signals before and optionally also after the temporary switchover.

Radio receiver with masking of switchover noise

In a circuit arrangement for deriving a binary signal from an alternating voltage (U), in which the alternating voltage can be delivered via a capacitor to the input of a threshold value circuit and a reference voltage obtained by integration serves to adjust the operating point at the input, an up/down counter is provided for deriving the reference voltage, its counting direction being controllable by the binary signal. From the output signal of the up/down counter, a further binary signal is derived, which after integration forms the reference voltage. The circuit is suitable for use in evaluating the data subcarrier component of a Radio Data System (RDS) signal, as defined by European Broadcasting Union (EBU) Technical Standard 3244-E.

Binary signal generator for RDS radio receiver

Pulses of constant pulse frequency but varying duty cycle are generated in a pulse generator which provides pulse trains or pulse sequences, as controlled by a pulse train or pulse length or sequence control unit coupled to the pulse generator and controlling the pulse generator to emit a train or sequence of pulses of similar pulse lengths, and further including a pulse length modulation control unit (12) coupled to the pulse generator and to the pulse train or sequence control unit, to control the length of the pulses of the individual pulse trains, the pulse lengths increasing in sequential pulse trains to provide an output signal of increasing intensity. The output from the pulse generator is filtered with respect to the base frequency, for example 800 Hz, and generated square wave pulses are converted into sawtooth wave pulses by a RC circuit to increase the dynamic range of output obtainable. The pulse generator (10), the pulse train length control unit (11) and the pulse length modulation control unit (12) can all form part of a digital microprocessor, generating the pulses, with intervening intervals to provide for a warning tone rhythm, the intervening intervals permitting the microprocessor to carry out calculating functions other than pulse generation for the warning tone.

Warning tone signal generator

Sixteen bit messages for selectively controlling receivers either to switch on an apparatus or to switch that apparatus off are transmitted on a format in which sixteen zeros are first transmitted, then a Willard sequence, then a control command, and then sixteen ones. The control command contains, in order of transmission, seven check bits, a control bit, seven address bits and a parity bit. The check bits are obtained by Nordstrom-Robinson coding from the eight data bits which consist of the seven address bits and a control bit, with cyclical rotation of the address bits but non-cyclical treatment of the control bit for deriving the seven check bits, with the result that, because the check bits and the control bit are received first, only three eight bit registers, each used twice first with the check bits as content and then with the address bits and the parity bit as content, are necessary for decoding at the receivers. The check bit comparison detects whether an on command or an off command is still possible and in one of those cases, treats the check bits as reversed in accord with the Nordstrom-Robinson coding, by the sign of the control bit.

Remote control system for selectively activating and inactivating

To provide a synthesized tuning frequency to control the local oscillator in a superheterodyne receiver, a frequency generating circuit includes a reference oscillator which provides a reference frequency which is frequency-divided to generate a plurality of divided sub-frequencies which, with respect to the reference frequency have at least a flank which is non-coincident with respect to corresponding flanks of other frequencies. These divided frequencies are added in an adder, the addition of which is controlled in accordance with a tuning command stored in a digital memory. Preferably, the adder is a NOR-gate to which selected frequencies are connected, selected by NAND-gates in accordance with a number provided by a digital tuning control and stored in the digital memory. The synthesized frequency is then used to provide an error control signal within a control loop connected to the local oscillator.

Digital tuner for a communication receiver, typically an AM receiver

A signal frequency, controlled by the output of a phase comparator, is obtained from a constant or reference signal frequency source by means of a frequency divider, the division ratio of which is voltage-controlled and variable, the control signal being obtained from the output of the phase comparator, in digital, or analog form. When in analog form, a monostable multivibrator is interposed so that a voltage-controlled divider having a division ratio of an average, predetermined factor can be used. The signal, the frequency of which is to be identified, is applied as one input to the phase comparator for comparison with the output signal from the frequency divider, the comparison providing the aforementioned division control signal.

Phase locked loop

Frequencies which respectively identify a particular transmitter, and a particular program content, and which are in a very low frequency range (from between 20 to 125 kHz can be recognized, and ditigal output control signals derived representative of whether one, or both, or none of these frequencies are present by use of a frequency selection input circuit, controlled by a change-over switch to initially select recognition of the transmitter identification which, if positive, is applied through a storage circuit having a storage time substantially longer than the switch-over rate, to provide an output signal if the selected transmitter is recognized, and hold that output signal during switch-over of the program content identification signal which, if present, will be fed back through a logic circuit to hold the output of the transmitter identification circuit as identified, and if not present, permit continued switch-over of the frequency identification circuit to continue to store transmitter identification signals, if present, but permit these signals to disappear, after the storage time, if the transmitter identification signals also cease. The time delay and storage circuit preferably include operational amplifiers, and the frequency identification circuit includes a phase-locked loop.

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Hildesheim, Germany

Wilhelm Hegeler