International Business Machines Corporation

Wilhelm Ernst Haller

Ulrich Krauch

Klaus J Getzlaff

Rolf Sautter

Holger Wetter

Kurt Lind

Elmar Gaugler

Friedhelm Kessler

Eric M Schwarz

Markus Kaltenbach

Christian Zoellin

Nicolas Maeding

Friedrich Schroeder

Christoph W Wandel

Steven R Carlough

Wen H Li

Thomas Ludwig

Ulrich Weiss

Johann Hajdu

Alexander Albert Woerner

Manuel Beck

Gunter Gerwig

Matthias Klein

Dieter F Wendel

Erwin F Pfeffer

Ute Gaertner

Maarten Jakob Boersma

Hans-Werner Tast

Jens Leenstra

Tobias Werner

Ricardo H Nigaglioni

Son Dao Trong

Lukas Daellenbach

Dietmar Schmunkamp

Ralf Richter

Ralph C Koester

Stefan Zimmermann

George Diedrich Gristede

Udo Wille

Guenter Mayer

Friedrich-Christian Wernicke

Monika Strohmer

Joachim Fenkes

Klaus Thumm

Herbert Chilinski

Mark D Mayo

Harald Mielich

Juergen Haas

Thomas Pfluger

Brigitte Roethe

Armin Windschiegl

Hartmut Sturm

Michael Haase

Wolfgang Bultmann

Alexander W&ouml;rner

Birgit Withelm

Robert Braun

A circuit is provided for addition of multiple binary numbers. The circuit includes a 4-to-2-compressor configured for calculating a compressed representation from four binary numbers received via operand inputs of the 4-to-2-compressor. The 4-to-2-compressor includes a first sub-circuit and a second sub-circuit. Each of the first sub-circuit and the second sub-circuit is configured for transmitting a bitwise inverted representation, of a compressed representation, from three binary numbers.

Circuit for addition of multiple binary numbers

An integrated circuit chip includes at least two integrated circuits, at least three scan chains, and a multiplexor circuitry. Each integrated circuit includes an integrated circuit input port and an integrated circuit output port. The scan chains and the integrated circuits are coupled by default with a series chain having integrated circuits and scan chains alternating each other. The series chain starts with an initial scan chain and ends with the end scan chain. Each scan chain except the initial one includes a first scan chain input port coupled by default with the integrated circuit output port of the respective adjacent integrated circuit. Each scan chain except the end one includes a first scan chain output port coupled by default with the integrated circuit input port of the respective adjacent integrated circuit.

Integrated circuit chip and a method for testing the same

An end point report for a design of an electronic circuit may be analyzed. Results of a static timing analysis run are loaded, a path from the loaded results is selected, and technology specific context data is provided. Additionally, a determination is made for every test point of the selected path of design quality parameters for determining a design problem area, and a determination is made for every design problem area, of a root cause by analyzing design problem area data in comparison to related ones of the technology specific context data.

Detecting circuit design flaws based on timing analysis

An improved method for fixing an early mode slack in a hierarchically designed hardware device with at least one source macro, an integration unit and at least one sink macro comprises: Loading hardware design timing data to determine pins where an early mode slack fix can be applied to fix an early mode slack; for each such pin determining a location across the design hierarchy for the early mode slack fix by calculating a weight value for each of a selection of fix locations of the early mode slack based on absolute values of arrival times of data signals, ratio and difference between arrival times of late mode data signals and early mode data signals; and assigning the early mode slack fix to the determined location based on said weight value.

Method and system to fix early mode slacks in a circuit design

The invention relates to a method and a system for repartitioning a formalized hardware description of a hierarchically structured electronic circuit design unit comprising a plurality of macros in terms of latch macros and combinatorial macros. In a first step, each macro is dissected into latch macros and signal cones in such a way that

Method and system for repartitioning a hierarchical circuit design

A method to generate a magnitude result of a mathematic operation of two decimal operands within one cycle in a decimal arithmetic logic unit structure, wherein the decimal operands are in hexadecimal sign magnitude format.

Method and decimal arithmetic logic unit structure to generate a magnitude result of a mathematic

The invention relates to a method and a system for repartitioning a formalized hardware description of a hierarchically structured electronic circuit design unit comprising a plurality of macros in terms of latch macros and combinatorial macros. In a first step, each macro is dissected into latch macros and signal cones in such a way that Subsequently, combinatorial macros are created by merging combinatorial signal cones along unit signal paths.

A computerized method, data processing system and computer program product reduce noise for a buffered design of an electronic circuit which was already placed and routed. For all areas between a power stripe and a ground stripe (half bay) in the design, the shapes are divided in different criticality levels. The shapes are rearranged based on their criticality level such that shapes with higher criticality level are placed closer to the stripes than those with lower criticality level.

Early noise detection and noise aware routing in circuit design

The invention relates to a method and a system for placing macros of a multilevel hierarchical description of a design unit on a chip. The method starts off by repartitioning the macro structure of the design unit into a set of latch macros and a set of combinatorial macros. By definition, a combinatorial macro is constructed in such a way that it contains no latches, and a latch macro contains latches and is constructed in such a way that each primary input/output of the latch macro coincides with an input or an output of a latch within said latch macro. After repartitioning the macro structure, the latch macros are synthesized within temporary boundaries and placed on the chip. Subsequently, the combinatorial macros are sequentially placed within a temporary boundary and synthesized one by one.

Method and system for placement of electronic circuit components in integrated circuit design

A system for creating layout and wiring diagrams for an integrated circuit (IC) includes a placement engine configured to receive a hierarchical schematic and to create a placed layout. The system also includes a flat layout engine configured to receive the hierarchical schematic and to create a flat layout and a back annotation engine coupled to the placement engine and the flat layout engine, the back annotation engine configured to receive the hierarchical placed layout and the flat unplaced layout and to create a flat placed layout there from.

Fast routing of custom macros

A method for implementing an adder including receiving a first and second operand. A sum of one or more corresponding digits from the first operand and the second operand is calculated. The calculating is performed by a plurality of adder blocks. Output from the calculating includes the sum of the corresponding digits and a carry out indicator for the corresponding digits. The sums of the corresponding digits and the carry out indicators in a carry chain are stored in an intermediate result register. Each of the sums in the intermediate result register is incremented by one. A selection between each of the sums and the sums incremented by one is performed. Input to the selecting includes the carry chain, and the output from the selecting includes a final sum of the first operand and the second operand. The final sum is stored in an output register.

System and method for providing a double adder for decimal floating point operations

A digital adder circuit comprising a plurality of logical stages in the carry logic of said adder circuit, for generating and propagating predetermined groups of operand bits, each stage implementing a predetermined logic function and processing input variables from a preceding stage and outputting result values to a succeeding stage static and dynamic logic in the carry network of a 4-bit adder, and with output from the first stage fed directly as an input () to the third stage of the carry network. Preferably, stages having normally relatively high switching activities are implemented in static logic. Preferably, the first stage of its carry network is implemented in a static logic, and the rest of the stages in dynamic logic.

Adder structure with midcycle latch for power reduction

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Remshalden, Germany

Wilhelm Ernst Haller