International Business Machines Corporation

Globalfoundries Inc.

Siemens Aktiengesellschaft

Tel Aviv University

Wilfried Haensch

Davood Shahrjerdi

Ghavam G Shahidi

Tak H Ning

Ali Khakifirooz

Effendi Leobandung

Dechao Guo

Robert H Dennard

Jin Cai

Bahman Hekmatshoartabari

Tenko Yamashita

Tayfun Gokmen

Kangguo Cheng

Keith Kwong Hon Wong

Stephen W Bedell

Chun-chen Yeh

Josephine B Chang

Shu-Jen Han

Hussein Ibrahim Hanafi

Devendra K Sadana

Veeraraghavan S Basker

Kevin K Chan

Andres Bryant

Amlan Majumdar

Jeffrey W Sleight

Toshiharu Furukawa

Katherine Lynn Saenger

Xin Ru Wang

Roy Rongqing Yu

Lior Horesh

Seyoung Kim

Anthony I Chou

Anirban Basu

Zhibin Ren

Bahman Hekmatshoar-Tabari

Yanfeng Wang

Mark Steven Squillante

Tomasz J Nowicki

Malte Johannes Rasch

Gan Wang

Dinkar Virendra Singh

Vasileios Kalantzis

Bruce Bennett Doris

Michael A Guillorn

Fei Liu

Kerry Bernstein

Huiming Bu

Chai Wah Wu

Steven John Koester

Daniel J Jaeger

Yu Lu

Rick L Mohler

Oguzhan Murat Onen

Wayne S Berry

Zihong Liu

Edward J Nowak

Takashi Ando

Choonghyun Lee

Theodorus E Standaert

Rajiv V Joshi

Terence B Hook

Isaac Lauer

Christian Lavoie

Bin Yang

Paul Michael Solomon

Arvind Kumar

Chung-Hsun Lin

Cheng-Wei Cheng

Zhen Zhang

Dirk Pfeiffer

Kuen-Ting Shiu

Pranita Kulkarni

Min Yang

Keith Aelwyn Jenkins

Louis C Hsu

Xinhui Wang

Mark B Ketchen

Werner A Rausch

Brian L Ji

Xiaoyan Shao

Udo Schwalke

Manjul Bhushan

Robert J Miller

Heinrich Zeininger

Christoph Zeller

Christine Qiqing Ouyang

Leland Chang

Eren Kursun

Meikei Ieong

Balasubramanian S Haran

Phaedon Avouris

James Bowler Hannon

Chen-Yong Cher

Huiling Shang

Wenjuan Zhu

Norma Edith Sosa Cortes

Hyung-Min Lee

Haim Avron

David R Motschman

Stefano Ambrogio

A system includes a processor, and a resistive processing resistive processing unit coupled to the processor. The resistive processing unit includes an array of cells, wherein the cells respectively include resistive devices, wherein at least a portion of the resistive devices are programmable to store weight values of a given matrix in the array of cells. When the given matrix is stored in the array of cells, the processor is configured to perform a weight extraction process. The weight extraction process applies a set of input vectors to the resistive processing unit to perform analog matrix-vector multiplication operations on the stored matrix, obtains a set of output vectors resulting from the analog matrix-vector multiplication operations, and determines weight values of the given matrix stored in the array of cells utilizing the set of input vectors and the set of output vectors.

Extraction of weight values in resistive processing unit array

Techniques are provided to implement hardware accelerated computing of eigenpairs of a matrix. For example, a system includes a processor, and a resistive processing unit coupled to the processor. The resistive processing unit includes an array of cells which include respective resistive devices, wherein at least a portion of the resistive devices are tunable to encode values of a given matrix which is storable in the array of cells. When the given matrix is stored in the array of cells, the processor is configured to determine an eigenvector of the stored matrix by executing a process which includes performing analog matrix-vector multiplication operations on the stored matrix to converge an initial vector to an estimate of the eigenvector of the stored matrix.

Hardware acceleration for computing eigenpairs of a matrix

A method is presented for computing an equilibrium distribution of Markov processes. The method includes storing weight values in an analog crossbar array of transition probability matrices, where the analog crossbar array of transition probability matrices represents a weight matrix with m rows and n columns, computing an eigenvector associated with a real eigenvalue of modulus one for each of the transition probability matrices, applying a gradient-based eigenvalue solver to converge to a dominant eigenpair, and determining a probability of changing from one state to another state in a stochastic entity based on outcomes of the gradient-based eigenvalue solver.

Markov processes using analog crossbar arrays

Methods and systems for solving a linear system include setting resistances in an array of settable electrical resistances in accordance with values of an input matrix. A series of input vectors is applied to the array as voltages to generate a series of respective output vectors. Each input vector in the series of vectors is updated based on comparison of the respective output vectors to a target vector. A solution of a linear system is determined that includes the input matrix based on the updated input vectors.

Analog hardware matrix computation

A 4D device comprises a 2D multi-core logic and a 3D memory stack connected through the memory stack sidewall using a fine pitch T&J connection. The 3D memory in the stack is thinned from the original wafer thickness to no remaining Si. A tongue and groove device at the memory wafer top and bottom surfaces allows an accurate stack alignment. The memory stack also has micro-channels on the backside to allow fluid cooling. The memory stack is further diced at the fixed clock-cycle distance and is flipped on its side and re-assembled on to a template into a pseudo-wafer format. The top side wall of the assembly is polished and built with BEOL to fan-out and use the T&J fine pitch connection to join to the 2D logic wafer. The other side of the memory stack is polished, fanned-out, and bumped with C4 solder. The invention also comprises a process for manufacturing the device. In another aspect, the invention comprises a 4D process and device for over 50&#xd7; greater than 2D memory density per die and an ultra high density memory.

Four D device process and structure

Mechanisms are provided for acceleration of convolutional neural networks on analog arrays. Input ports receive image signals from frames in an input image. Input memory arrays store the image signals received from the input ports into a respective input memory location to create a plurality of image sub-regions in input memory arrays. A distributor associated each of a set of analog array tiles in an analog array to a part of image sub-regions of the input memory arrays, so that one or more of a set of analog memory components is associated with the image signals in a distribution order to create a respective output signal. An assembler stores each of the respective output signals into one of a set of memory outputs in an output order that is determined by the distribution order.

Acceleration of convolutional neural networks on analog arrays

A computer-implemented method executed on a processor for detecting whether a wafer has been tampered during a semiconductor fabrication process, the method including, at a plurality of patterning steps where lithographic patterns are defined and etched or at a plurality of fabrication processing steps, marking, via an identification tool, each die with an unclonable identification in a memory array, inspecting, via an inspection tool, each of the dies, and removing compromised wafers from a wafer pool during the semiconductor fabrication process.

Inspection and identification to enable secure chip processing

A computer-implemented method for Eigenpair computation is provided. The method includes computing, her a hardware processor, an Eigenvector and respective Eigenvalues of the Eigenvector of a matrix by using a modified Stochastic Optimization process including performing a matrix vector product on a Resistive Processing Unit (RPU) crossbar array operatively coupled to the hardware processor and performing a scalar vector product on a digital device operatively coupled to the hardware processor and representing, for each of an Eigenpair, an initial guess for the Eigenvector and the respective Eigenvalues. The computing step includes storing the matrix in the RPU crossbar array.

Eigenvalue decomposition with stochastic optimization

Embodiments of the present invention include a crossbar array that includes a resistive processing unit (RPU) device at each crosspoint in the crossbar array. The RPU device includes a single weight storage element, and multiple weight reader elements. A first weight reader element is coupled with a first row wire to compute a first matrix product value using a first value and a stored value, the first value being transmitted via the first row wire and the stored value being stored in the single weight storage element. A second weight reader element is coupled with a second row wire to compute a second matrix product value of a second value and said stored value, the second value being transmitted via the second row wire.

Resistive processing unit with multiple weight readers

Photovoltaic devices such as solar cells having one or more field-effect hole or electron inversion/accumulation layers as contact regions are configured such that the electric field required for charge inversion and/or accumulation is provided by the output voltage of the photovoltaic device or that of an integrated solar cell unit. In some embodiments, a power source may be connected between a gate electrode and a contact region on the opposite side of photovoltaic device. In other embodiments, the photovoltaic device or integrated unit is self-powering.

Field-effect photovoltaic elements

Devices and methods are provided to construct resistive random-access (RRAM) array structures which comprise RRAM memory cells, wherein each RRAM memory cell is formed of multiple parallel-connected RRAM devices to reduce the effects of resistive switching variability of the RRAM memory cells.

Resistive random-access memory array with reduced switching resistance variability

A system, comprising: a memory that stores computer-executable components; a processor, operably coupled to the memory, that executes the computer-executable components stored in the memory, wherein the computer-executable components comprise: an expression component that expresses the read current range in an RPU as read current Iwmin and Iwmax, a constant current source component that generates a reference current I, a computing component that subtracts the reference current value within from the read current value to generate an active net current read value that is negative, positive or null; a weighting component that analyzes the active current value and assigns it to a negative, positive or null weight.

Circuit methodology for differential weight reading in resistive processing unit devices

A method of forming a semiconductor structure is provided. The method including forming a first vertical channel on a first layer of source/drain material that is perpendicular relative to the first vertical channel, and forming a first source/drain semiconductor structure by removing one or more portions of the first layer of source/drain material such that i) the first source/drain semiconductor structure has a vertical side that is substantially planar with a vertical side of the first vertical channel and ii) a width of the source/drain is greater than a width of the first vertical channel, wherein the first source/drain semiconductor structure extends perpendicularly from its vertical side farther than the first vertical channel extends perpendicularly from its vertical side.

Semiconductor structure with an L-shaped bottom

Growing community of inventors

Somers, NY, United States of America

Wilfried Haensch