Intel Corporation

Wilfred Gomes

Abhishek A Sharma

Rajesh Kumar

Mauro J Kobrinsky

Doug B Ingerly

Mark T Bohr

Tahir Ghani

Ravindranath Vithal Mahajan

Kinyip Phoa

Van H Le

Swaminathan Sivakumar

Pooya Tadayon

Sagar Suthram

Robert L Sankman

Uygar E Avci

Bernhard Sell

Rajabali Koduri

Anand S Murthy

Debendra Mallik

Hui Jae Yoo

Sanka Ganesan

Elliot Tan

Travis W LaJoie

Kevin Fischer

Pushkar Ranade

Abhishek Anil Sharma

Glenn J Hinton

Omkar G Karhade

Nitin A Deshpande

Fatih Hamzaoglu

Harish Krishnamurthy

Nachiket Venkappayya Desai

Conor P Puls

Wesley D McCullough

Leonard M Neiberg

James D Waldemer

Wesley D Mc Cullough

Jack T Kavalieros

Robert S Chau

Altug Koker

Gilbert W Dewey

Marko Radosavljevic

Brian S Doyle

Johanna M Swan

Adel A Elsherbini

Han Wui Then

Sujit Sharan

Telesphor Kamgaing

Rishabh Mehandru

Paul B Fischer

Kemal Aygun

Cheng-Ying Huang

Kimin Jun

Zhiguo Qian

Nicole K Thomas

Mathew J Manusharow

Szuya S Liao

Cory E Weber

Ashish Agrawal

Ram S Viswanath

Digvijay Ashokkumar Raorane

Rajasekaran Swaminathan

Mark Armstrong

Andrew Paul Collins

Miriam Ruth Reshotko

Chieh-Jen Ku

Pei-Hua Wang

Sriram Srinivasan

Richard J Dischler

Adrian C Moga

Yidnekachew S Mekonnen

Jeff C Morriss

Christopher M Pelto

Beomseok Choi

Mark C Phillips

Nevine Nassif

Juan G Alzate-Vinasco

Yu Amos Zhang

Eduard Roytman

Albert Chen

Abhishek Sharma

Pulkit Jain

Pratik Koirala

Udi Sherel

Alekhya Nimmagadda

Tushar Talukdar

Matthieu Giraud-Carrier

Embodiments of an integrated circuit (IC) die comprise a first region having a first surface and a second surface, the first surface being orthogonal to the second surface; a second region comprising a semiconductor material, the second region attached to the first region along a first planar interface that is orthogonal to the first surface and parallel to the second surface; and a third region comprising optical structures of a photonic IC, the third region attached to the second region along a second planar interface that is parallel to the first planar interface. The first region comprises: a plurality of layers of conductive traces in a dielectric material, each layer of the conductive traces being parallel to the second surface such that the conductive traces are orthogonal to the first surface; and bond-pads on the first surface, the bond-pads comprising portions of respective conductive traces exposed on the first surface.

Package architecture of photonic system with vertically stacked dies having planarized edges

Embodiments of a microelectronic assembly comprise: a plurality of microelectronic sub-assemblies arranged in a coplanar array, each microelectronic sub-assembly having a first side and an opposing second side; a first conductive plate coupled to the first sides of the microelectronic sub-assemblies; and a second conductive plate coupled to the second sides of the microelectronic sub-assemblies. The first conductive plate and the second conductive plate comprise sockets corresponding to each of the microelectronic sub-assemblies, and each microelectronic sub-assembly comprises a first plurality of integrated circuit (IC) dies coupled on one end to a first IC die and on an opposing end to a second IC die; and a second plurality of IC dies coupled to the first IC die and to the second IC die.

Package architecture of scalable compute wall having compute bricks with vertically stacked dies

In one embodiment, an apparatus comprises: a plurality of banks to store data; and a plurality of interconnects, each of the plurality of interconnects to couple a pair of the plurality of banks. In response to a data movement command, a first bank of the plurality of banks is to send data directly to a second bank of the plurality of banks via a first interconnect of the plurality of interconnects. Other embodiments are described and claimed.

Performing distributed processing using distributed memory

Methods and apparatus to implement an integrated circuit to operate based on data access characteristics. For example, the integrated circuit comprises a first array comprising a first plurality of memory cells, a second array comprising a second plurality of memory cells, and both first and second arrays to store data of a processor. The second plurality of memory cells implements a selector transistor of a memory cell within using a thin-film transistor (TFT), and a memory control circuit is to write a first set of bits to the first array and a second set of bits to the second array upon determining the first set of bits is to be accessed more frequently than the second set of bits.

Embedded dynamic random-access memory (eDRAM) to operate based on data access characteristics

IC devices including angled transistors formed based on angled wafers are disclosed. An example IC device includes a substrate and a semiconductor structure. A crystal direction of a crystal structure in the semiconductor structure is not aligned with a corresponding crystal direction (e.g., having same Miller indices) of a crystal structure in the substrate. An angle between the two crystal directions may be 4-60 degrees. The semiconductor structure is formed based on another substrate (e.g., a wafer) that has a different orientation from the substrate, e.g., flats or notches of the two substrates are not aligned. The crystal direction of the semiconductor structure may be determined based on a crystal direction in the another substrate. The semiconductor structure may be a portion of a transistor, e.g., the channel region and S/D regions of the transistor. The semiconductor structure may be angled with respect to an edge of the substrate.

Integrated circuit devices with angled transistors formed based on angled wafers

Structures having ultra-high conductivity global routing are described. In an example, an integrated circuit structure includes a device layer having a plurality of transistors. A plurality of metallization layers is above the plurality of transistors of the device layer. One or more of the metal layers includes a material having a critical temperature greater than 10 Kelvin and less than 300 Kelvin.

Integrated circuit structures having ultra-high conductivity global routing

Memory device architectures including integrated high voltage planar transistor support circuitry underlying memory cell arrays are discussed related to improving density and device performance Such memory device architectures include planar transistors having wide band gap channel materials integrated with memory cell arrays using a number of metallization layers. The metallization layers between the planar transistors and the memory cells are predominantly tungsten and the metallization layers in which the memory cells are embedded are predominantly a metal other than tungsten.

Integrated planar transistors and memory cell array architectures

Three-dimensional hysteretic memory based on semiconductor nanoribbons is disclosed. An example memory cell may include a nanoribbon-based access transistor and a capacitor coupled to the access transistor, where the capacitor at least partially wraps around the nanoribbon in which the access transistor is formed. One or both of a gate stack of the access transistor and the capacitor insulator may include a hysteretic material/arrangement. Plurality of such memory cells may be provided in a single nanoribbon, and the nanoribbon may be one of a stack of nanoribbons provided above one another over a support structure. Incorporating hysteretic memory cells in different layers above a support structure by using stacks of semiconductor nanoribbons may allow significantly increasing density of hysteretic memory cells in a memory array having a given footprint area, or conversely, significantly reducing the footprint area of the memory array with a given density of hysteretic memory cells.

Three-dimensional nanoribbon-based hysteretic memory

Described herein are transistors with front-side and back-side routing, and IC devices including such transistors. The transistor includes a channel material having a longitudinal structure and formed in a dielectric material. A source region encloses a first portion of the channel material, a gate electrode encloses a second portion of the channel material, and a drain region encloses a third portion of the channel material. Each of the source region, gate electrode, and drain region have a first face and a second face opposite the first face, the first and second faces co-planar with the faces of the dielectric material. A first contact is coupled to the first face of the source region, and a second contact is coupled to the second face of the source region.

Transistor with front-side and back-side contacts and routing

In one embodiment, an integrated circuit package includes: a first die having a plurality of cores, each of the plurality of cores having a local memory interface circuit to access a local portion of a dynamic random access memory (DRAM); and a second die comprising the DRAM, where at least some of the plurality of cores are directly coupled to a corresponding local portion of the DRAM by a stacking of the first die and the second die. Other embodiments are described and claimed.

Providing fine grain access to package memory

Stitched dies having a cooling structure are described. For example, an integrated circuit structure includes a first die including a first device layer and a first plurality of metallization layers over the first device layer. The integrated circuit structure also includes a second die including a second device layer and a second plurality of metallization layers over the second device layer, the second die separated from the second die by a scribe region. A common conductive interconnection is coupling the first die and the second die at a first side of the first and second dies. A plurality of microfluidic channels is coupled to the first side of the first and second dies.

Cooling approaches for stitched dies

Embodiments of the present disclosure are based on using transistors with back-side contacts. Such transistors enable back-side power delivery to IC components (e.g., transistors, etc.) of an IC structure, which may be more advantageous than front-side power delivery in some implementations. Embodiments of the present disclosure are further based on recognition that using a glass support structure at the front side of an IC structure with back-side power delivery may advantageously reduce parasitic effects in the IC structure, e.g., compared to using a silicon-based support structure at the front.

Back-side power delivery with glass support at the front

Integrated circuit (IC) devices implementing bilayer memory stacking with compute logic circuits shared between bottom and top memory layers are disclosed. An example IC device includes a first IC structure that includes one or more memory layers but not necessarily compute logic circuits, the first IC structure being bonded with a second IC structure that includes at least one layer of compute logic circuits and further includes one or more memory layers stacked above the compute logic circuits. The first and second IC structures may be bonded so that the compute logic circuits of the second IC structure may be communicatively coupled to memory layers of both the first and second IC structures.

Bilayer memory stacking with computer logic circuits shared between bottom and top memory layers

Microelectronic assemblies fabricated using hybrid manufacturing with modified via-last process are disclosed. The fabrication approach is based on using hybrid manufacturing to bond first and second IC structures originally provided on different dies but filling at least portions of vias that are supposed to couple across a bonding interface between the first and second IC structures with electrically conductive materials after the IC structures have been bonded. A resulting microelectronic assembly that includes the first and second IC structures bonded together may have vias extending through all of the first IC structure and into the second IC structure, thus providing electrical coupling between one or more components of the first IC structure and those of the second IC structure, where an electrically conductive material in the individual vias is continuous through the first IC structure and at least a portion of the second IC structure.

Hybrid manufacturing with modified via-last process

An example IC device includes a frontend layer and a backend layer with a metallization stack. The metallization stack includes a backend memory layer with a plurality of memory cells with backend transistors, and a layer with a plurality of conductive interconnects (e.g., a plurality of conductive lines) and air gaps between adjacent ones of the plurality of interconnects. Providing air gaps in upper metal layers of metallization stacks of IC devices may advantageously reduce parasitic effects in the IC devices because such effects are typically proportional to the dielectric constant of a surrounding medium. In turn, reduction in the parasitic effects may lead to improvements in performance of, or requirements placed on, the backend memory.

Backend memory with air gaps in upper metal layers

Growing community of inventors

Portland, OR, United States of America

Wilfred Gomes