The University of Texas System

Other

Texas Instruments Corporation

Texas A&M University System

Wiley P Kirk

Bruce E Gnade

Meng Tao

Chih-Chen Cho

Robert M Wallace

Mark H Weichold

Joe X Zhou

William B Kinard

The present invention relates generally to compositions, kits and methods of providing improved semiconductor surfaces free of dangling bonds and free of strained bonds. One method provides for preventing interfacial reactions between a semiconductor surface and metal or dielectric comprising the steps of preparing a passivated semiconductor surface using a valence-mending agent and depositing a layer of metal or dielectric on the valence-mended semiconductor surface. As further described, a semiconductor surface free of interfacial reactions between the surface and a second molecular species may include a semiconductor surface with one atomic layer of valence-mending atoms, wherein valence mending occurs after introducing the semiconductor surface to a passivating agent. The present invention also includes a kit for preventing interfacial reactions from occurring on a semiconductor surface comprising a passivating agent and an instructional manual.

Suppression of chemical reactivity on semiconductor surfaces

The present invention relates generally to a method of improving the performance of solid state devices, and specifically provides methods for passivating a semiconductor surfaces with a monolayer of passivating material.

Monatomic layer passivation of semiconductor surfaces

A method of forming lattice matched single crystal wide bandgap II-VI compound semiconductor films over a silicon substrate includes first cleaning ( ) the silicon substrate. A passivation layer is formed ( ), which may comprise arsenic, germanium, or CaF , among others. The lattice matched layer is then grown ( ) on the passivation layer.

method of forming lattice matched layer over a surface of a silicon substrate

An anode plate (10) for use in a field emission flat panel display device (8) includes a transparent substrate (26) having a plurality of spaced-apart, electrically conductive regions (28) are covered by a luminescent material (24) and from the anode electrode. A getter material (29) of porous silicon is deposited on the substrate (26) between the conductive regions (28) of the anode plate (10). The getter material (29) of porous silicon is preferably electrically nonconductive, opaque, and highly porous. Included are methods of fabricating the getter material (29) on the anode plate (10).

Anode plate for flat panel display having silicon getter

A gated resonant tunneling diode has a semiconductor mesa formed on a semiconductor substrate, a tunneling barrier layer between the mesa and the substrate, and a gate layered over the substrate about the mesa and aligned in close proximity to the tunneling barrier layer. A control voltage on the gate laterally constricts a potential well in the tunneling barrier to control the electrical size of a channel within which tunnelling occurs across the tunneling barrier layer. Preferably the gate and the tunneling layer are disposed at the base of the mesa, and the gate makes a rectifying Schottky junction in connection with the tunneling barrier layer. The device is constructed using an anisotropic etch to form the mesa with an undercut wall and a top portion overhanging the undercut wall, and a nonconformal deposition of gate material to align the gate with the top portion of the mesa.

Growing community of inventors

College Station, TX, United States of America

Wiley P Kirk