Advanced Micro Devices Corporation

Other

Wiley Eugene Hill

Bin Yu

Haihong Wang

Shibly S Ahmed

Ming-Ren Lin

Todd P Lukanc

John JianShi Wang

Yider Wu

Jeffrey P Erhardt

Kurt Taylor

Chern-Jiann Lee

Mark Aaron Hill

James Leland Hill

Rithy Hang

A seafood handling tool is provided that comprises a tong-like configuration with a first arm member and a second arm member in pivotal relationship to one another. The arm members are connected to one another along their proximal ends via a clevis, which extends from the first arm member and supports the second arm member from a pin joint. The clevis offsets the first and second arm member, while the pin joint allows the arm members to pivot relative to one another to accept larger or smaller seafood between the arm members along the distal ends. The distal ends of the arm members include elongated tines that extend from the inner surfaces thereof and towards one another. The tines engage an article of seafood while the user grips the proximal ends of the arm members, thereby separating the seafood from the handler.

Fish gripping tool

A method of doping fins of a semiconductor device that includes a substrate includes forming multiple fin structures on the substrate, each of the fin structures including a cap formed on a fin. The method further includes performing a first tilt angle implant process to dope a first pair of the multiple fin structures with n-type impurities and performing a second tilt angle implant process to dope a second pair of the multiple fin structures with p-type impurities.

SRAM formation using shadow implantation

A memory device includes multiple fins formed adjacent to one another, a source region, a drain region, a gate, a wordline, and a bitline contact. At least one of the multiple fins is doped with a first type of impurities and at least one other one of the fins is doped with a second type of impurities. The source region is formed at one end of each of the fins and the drain region is formed at an opposite end of each of the fins. The gate is formed over two of the multiple fins, the wordline is formed over each of the multiple fins, and a bitline contact is formed adjacent at least one of the multiple fins.

A method for determination of tunnel oxide weakness is provided. A tunnel oxide layer is formed on a semiconductor wafer. At least one poly gate is formed on the tunnel oxide layer in a flash memory region of the semiconductor wafer. At least one poly island, which is substantially larger than the poly gate, is formed on the tunnel oxide layer in a voltage contrast cell region of the semiconductor wafer. The poly island and the tunnel oxide layer therebeneath form a voltage contrast tunnel oxide cell. A voltage contrast measurement is performed on the voltage contrast tunnel oxide cell. The voltage contrast measurement is then compared with prior such voltage contrast measurements on other such voltage contrast tunnel oxide cells. The tunnel oxide weakness of the tunnel oxide layer is then determined from the voltage contrast measurement comparisons.

In-line voltage contrast determination of tunnel oxide weakness in integrated circuit technology development

A method forms a semiconductor device from a device that includes a first source region, a first drain region, and a first fin structure that are separated from a second source region, a second drain region, and a second fin structure by an insulating layer. The method may include forming a dielectric layer over the device and removing portions of the dielectric layer to create covered portions and bare portions. The method may also include depositing a gate material over the covered portions and bare portions, doping the first fin structure, the first source region, and the first drain region with a first material, and doping the second fin structure, the second source region, and the second drain region with a second material. The method may further include removing a portion of the gate material over at least one covered portion to form the semiconductor device.

Method of forming merged FET inverter/logic gate

A semiconductor device includes an N-channel device and a P-channel device. The N-channel device includes a first source region, a first drain region, a first fin structure, and a gate. The P-channel device includes a second source region, a second drain region, a second fin structure, and the gate. The second source region, the second drain region, and the second fin structure are separated from the first source region, the first drain region, and the first fin structure by a channel stop layer.

Isolated FinFET P-channel/N-channel transistor pair

A memory device includes a conductive structure, a number of dielectric layers and a control gate. The dielectric layers are formed around the conductive structure and the control gate is formed over the dielectric layers. A portion of the conductive structure functions as a drain region for the memory device and at least one of the dielectric layers functions as a charge storage structure for the memory device. The dielectric layers may include oxide-nitride-oxide layers.

Flash memory device

A semiconductor device includes an N-channel device and a P-channel device. The N-channel device includes a first source region, a first drain region, a first fin structure, and a gate. The P-channel device includes a second source region, a second drain region, a second fin structure, and the gate. The second source region, the second drain region, and the second fin structure are separated from the first source region, the first drain region, and the first fin structure by an insulating layer.

Merged FinFET P-channel/N-channel pair

A method facilitates the doping of fins of a semiconductor device that includes a substrate. The method includes forming fin structures on the substrate, where each of the fin structures includes a cap formed on a fin. The method further includes performing a first tilt angle implant process to dope a first one of the fins with n-type impurities and performing a second tilt angle implant process to dope a second one of the fins with p-type impurities.

Systems and methods for forming dense n-channel and p-channel fins using shadow implanting

A variable design tool utilizes memory units to determine at which point a design rule fails. The variable design tool can provide a bit map indicating the points of failures for particular rules. The bit map can also be utilized to determine misalignment errors. The memory cells, typically SRAM units are arranged in 4&times;4 matrices which are arranged in four 16&times;16 matrices.

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Moss Beach, CA, United States of America

Wiley Eugene Hill