Arm Limited

Wilco Dijkstra

David James Seal

Simon Andrew Ford

Dominic Hugo Symes

David Walter Flynn

Stuart David Biles

Andrew Christopher Rose

Vladimir Vasekin

Stephen John Hill

David John Butcher

Michael Robert Nonweiler

A data processing system is provided that includes an instruction decoderresponsive to a compare and branch instruction CHKA.X that performs a comparison between first and second values stored in first and second registers Rn, Rm respectively. A target branch address is determined from a pre-programmed stored value and a branch to a sub-routine is performed in dependence upon a result of the comparison.

Compare and branch mechanism

The present invention provides a technique for swapping data values within a data word. In particular, a single endian reverse instruction is provided to cause independent swap operations to be performed on particular sections of an input data word. The data processing apparatus of the present invention comprises a data processing unit for executing instructions which is responsive to the endian reverse instruction to apply an endian reverse operation to an input data word Rm comprising a plurality of data values. The endian reverse operation yields a result data word Rd given by: treating the input data word as consisting of a plurality of input sections, the result data word having a corresponding plurality of result sections, at least one input section comprising a plurality of data values; and for at least one of the input sections comprising a plurality of data values, performing an independent swap operation on the data values within that input section to form the result data word Rd in which the corresponding result section has its data values swapped with respect to that input section. This provides a particularly efficient technique for providing endian reversal functionality within a data processing apparatus supporting a variety of data structures, such as packed halfwords, zero extended halfwords, sign extended halfwords, etc.

Data processing apparatus and method for utilizing endianess independent data values

A data processing apparatus () comprising: a register data store operable to store data elements; an instruction decoder () operable to decode an instruction with generated constant, said instruction having a data value associated therewith; a data processor () operable to perform data processing operations within parallel processing lanes on at least one source operand in response to a data processing instruction decoded by said instruction decoder (); and said data processor being operable in response to said decoded instruction with generated constant and associated data value to expand at least a data portion () of said associated data value, said expansion being performed in response to said instruction with generated constant and depending on a selected function, to generate a constant (), said generated constant () forming one of said at least one source operands.

Method and apparatus for constant generation in SIMD processing

Data processing apparatus and method perform data processing operations on floating point data elements. The data processing apparatus has processing logic for performing data processing operations on the floating point data elements, and decode logic operable to decode a data processing instruction in order to determine a corresponding data processing operation to be performed by the processing logic. The data processing instruction has an m-bit immediate value encoded therein. Further, constant generation logic is provided to perform a logical operation on the m-bit immediate value in order to generate an n-bit floating point constant for use as at least one input floating point data element for the processing logic when performing the corresponding data processing operation. The values 'n' and 'm' are integers, and n is greater than m. This approach provides a particularly efficient technique for generating floating point constants.

Data processing apparatus and method for performing data processing operations on floating point data elements

A data processing system includes an instruction fetching circuit, an instruction queueand further processing circuits. A branch target cache, which maybe a branch target address cache, a branch target instruction cacheor both, is used to store branch target addresses or blocks of instructions starting at the branch target respectively. A control circuitis responsive to the contents of the instruction queuewhen a branch instruction is encountered to determine whether or not storage resources within the branch target cacheshould be allocated to that branch instruction. Storage resources within the branch target cachewill be allocated when the number of program instructions within the instruction queue is below a threshold number and/or the estimated execution time of the program instructions is below a threshold time.

Allocation of branch target cache resources in dependence upon program instructions within an instruction queue

When performing data processing operations upon data words including a plurality of abutting data values a , a , a , a , b , b , b and b the results of the operation upon one data value may influence a neighboring data value in an undesired manner. An error correcting value may be determined from the input data words and then combined with the intermediate result to correct for any undesired interactions between adjacent data values.

Parallel processing of multiple data values within a data word

The present invention provides a method, data processing system and computer program for comparing first and second floating point numbers involving providing a hierarchy of tests arranged to identify from said first and second floating point numbers whether said one or more exception conditions exist. Each test is arranged to generate a hit signal if that test predicts that one or more exception conditions exist. If the executed test generates a hit signal and is not the final test in the hierarchy, the method branches to the next test in the hierarchy, executes that test and returns to the step of determining whether the executed test has generated a hit signal. If the executed test generates a hit signal and is the final test in the hierarchy, an exception signal is generated indicating the presence of one or more exception conditions.

Method, data processing system and computer program for comparing floating point numbers

A clipping and quantization technique is described for producing clipped numbers in a range of 0 to N&minus;1 (from unclipped numbers in a range of &minus;0.5N to (1.5N&minus;1)), where N is 2 and m is the bit length of the desired clipped and quantized number. The most significant bit of the unclipped data value indicates whether an overflow of the permitted range has occurred and that clipping is required. The next most significant bit (m&minus;1 ) indicates which saturated value should be adopted. These properties of the unclipped data value may be exploited to generate the desired clipped and quantized numbers using logical left shifting and conditionally executed saturating instructions executing upon a general purpose processor The shifting operations performed to achieve saturation operation may simultaneously yield quantization.

Clipping data values in a data processing system

A data processing system and method are provided for generating a structured listing of symbols from which encoded data values for those symbols can be determined. The data processing system comprises a list generator for generating from an input stream of symbols a first list having a plurality of entries, each entry identifying a symbol in the input stream and the frequency with which that symbol appears. A sorter is then arranged to order the entries in the first list by frequency, and a selector is arranged to select the two symbols having the lowest frequency. A new symbol generator, responsive to the selector, is used to generate a new symbol to represent the two selected symbols, and to allocate the new symbol a frequency based on the two selected symbols. The list generator is also arranged to generate a second list for storage of new symbols generated by the new symbol generator, the list generator being arranged to store the new symbol as an entry in the second list along with an indication of the frequency allocated to the new symbol. Further, the list generator makes unavailable for subsequent steps in the generation of the structured listing the entries for the two symbols selected by the selector. The selector and new symbol generator are arranged to repetitively represent the two symbols having the lowest frequency with a new symbol until only one available entry remains, each new symbol being stored in the second list, and in each iteration the selector being arranged to select the two symbols from all available entries in the first and the second list. Using this technique, the time taken to generate the structured listing increases proportional to N, where N is the number of symbols in the input stream.

Data processing system and method for generating a structured listing of symbols

A system and method are provided for organizing and managing a tree structure having a plurality of nodes representing physical entities, the tree structure defining a number of node locations, each node location being reached via a predetermined path from a root node of the tree structure. The method comprises the steps of associating first and second keys with each node to be included in the tree structure, the value of at least the first key being unique for each node, and then arranging the nodes within the tree structure by sorting the nodes with respect to both the first key and the second key, the sorting with respect to the first key being such that each node may be positioned within the tree structure at any node location along the path from the root node to the node location specified by the first key. By this approach, a search can be performed for a node within the tree structure based on specified criteria for both the first and second keys.

System and method of organizing nodes within a tree structure

Disclosed is a data processing system and a method for performing an arithmetic operation on a plurality of signed data values. In the data processing system and the method, there is a first step in which two or more signed data values are encoded into a composite value and an arithmetic operation is applied to the composite value to produce an encoded result. The encoded result can then be decoded to produce final results where each final result represents the application of the arithmetic operation to a corresponding signed data value. Thus, by using the encoded composite value, a single arithmetic operation can be applied simultaneously to multiple data values and the result then decoded. The decoded result represents the result of applying the arithmetic operation to each data value separately. The advantage of this operation is that operations can be formed on multiple data values without requiring the provision of dedicated hardware or new instructions as required by the prior art.

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Cambridge, United Kingdom

Wilco Dijkstra