International Business Machines Corporation

Wilbur David Pricer

Kenneth Joseph Goodnow

William R Tonti

Sebastian Theodore Ventrone

Michel S Michail

Claude Louis Bertin

Kerry Bernstein

Alfred Grill

Katherine Lynn Saenger

Thomas M Shaw

Deborah A Neumayer

Charles Thomas Black

Alvar Antonio Dean

John Anthony Bracchitta

James William Adkisson

Randy William Mann

William A Klaasen

Anthony K Stamper

Andres Bryant

Russell J Houghton

Jack Allan Mandelman

Tak H Ning

John J Ellis-Monaghan

John Atkinson Fifield

Clarence Rosser Ogilvie

Anthony Richard Bonaccio

William Thomas Motsiff

William J Cote

Thomas Benjamin Faure

Kurt R Kimmel

Edward J Nowak

Erik L Hedberg

John E Gersbach

Minh H Tong

Bernard S Meyerson

Charles Arthur Whiting

Patrick Edward Perry

Stephen William Mahin

Daniel C Edelstein

Steven H Voldman

Cyril Cabral, Jr

Timothy Jay Dell

Richard Quimby Williams

William F Clark, Jr

Wayne John Howell

Mark William Kellogg

Scott Whitney Gould

Robert Michael Geffken

Thomas M Maffitt

Rosemary A Previti-Kelly

Edward P Maciejewski

Marc Raymond Faucher

Peter Edwin Cottrell

Paul T Gutwin

Madhukar L Joshi

Michael P Clinton

John W Goetz

Cecilia C Smolinski

James Earl Selleck

J Alex Chediak

Jeffrey P Gambino

Ramachandra Divakaruni

Jed Hickory Rankin

Terence B Hook

Wendell P Noble

Gary Bela Bronner

Ning Lu

Janak G Patel

Lawrence G Heller

Steven J Tanghe

Satya N Chakravarti

Hsing-San Lee

Francis W Wiedman, Iii

Paul M Fahey

Norbert G Vogl, Jr

Dana J Thygesen

William Robert Patrick Tonti

Sabastian Theodore Ventrone

Janak Ghanshyambhai Patel

Richard K Mason

Azzouz Nezar

A method of forming an integrated ferroelectric/CMOS structure which effectively separates incompatible high temperature deposition and annealing processes is provided. The method of the present invention includes separately forming a CMOS structure and a ferroelectric delivery wafer. These separate structures are then brought into contact with each and the ferroelectric film of the delivery wafer is bonded to the upper conductive electrode layer of the CMOS structure by using a low temperature anneal step. A portion of the delivery wafer is then removed providing an integrated FE/CMOS structure wherein the ferroelectric capacitor is formed on top of the CMOS structure. The capacitor is in contact with the transistor of the CMOS structure through all the wiring levels of the CMOS structure.

Flip FERAM cell and method to form same

A decoupling capacitor is provided for a semiconductor device and may include a first low dielectric insulator layer and a low resistance conductor formed into at least two interdigitized patterns on the surface of the first low dielectric insulator in a single interconnect plane. A high dielectric constant material may be provided between the two patterns. A circuit for testing a plurality of these capacitors is also provided which includes a charge monitoring circuit, a coupling circuit and a control circuit.

Intralevel decoupling capacitor, method of manufacture and testing circuit of the same

Method of manufacturing an intralevel decoupling capacitor

A method and system for providing communication between electronic devices that uses the phase of data transmitted between the devices to indicate logical one and zero values. The method and system has the added benefit of relieving the traditional limitations of voltage communication restraints between devices having differing core voltages (i.e. Differing generations).

Method and apparatus for providing communication between electronic devices

A way of dynamically modifying error recovery on a communications controller to operate at the lowest power mode allowed by current error rate conditions. When operating conditions are good and a small number of errors are detected, a low power error detection/correction mode is entered saving battery life. The low power error correction mechanism runs at a slower frequency and lower power than the high power mechanism and maintains the same data rate for the controller, thus saving power. Selecting the controller error (power) mode may be externally, such as by a person using a control dial on a cellular telephone when the voice data gets too noisy. Alternatively, the selection can be automatic, a critical error level detector internally making the selection.

Low-power critical error rate communications controller

A method and structure for forming an emitter in a vertical bipolar transistor includes providing a substrate having a collector layer and a base layer over the collector layer, forming a patterning mask over the collector layer, and filling openings in the mask with emitter material in a damascene process. The CMOS/vertical bipolar structure has the collector, base regions, and emitter regions vertically disposed on one another, the collector region having a peak dopant concentration adjacent the inter-substrate isolation oxide.

Logic SOI structure, process and application for vertical bipolar transistor

An integrated ferroelectric/CMOS structure which comprises at least a ferroelectric material, a pair of electrodes in contact with opposite surfaces of the ferroelectric material, where the electrodes do not decompose at deposition or annealing, and an oxygen source layer in contact with at least one of said electrodes, said oxygen source layer being a metal oxide which at least partially decomposes during deposition and/or subsequent processing is provided as well as a method of fabricating the same.

Feram cell with internal oxygen source and method of oxygen release

A method and structure for blowing a fuse including removing an insulator above a fuse link and etching the fuse link.

Inductive fuse for semiconductor device

Disclosed is a system and method for eliminating the unnecessary toggling of logic in a logic network. The method and system can be incorporated directly into logic synthesis software, or may be implemented manually. Provided is a mechanism for identifying critical nets and then inserting net latches at the critical nets wherein each net latch is controlled by an enable signal that also controls a related output latch. Each net latch is comprised of a circuit which can on command hold static the last logic level on a given logic node.

Logic power optimization algorithm

An IC chip comprising, a nearby or remote source capable of particle emissions; circuitry formed in the IC chip that is adversely affected by impacts of particle emissions from said source; and a particle detector formed in the IC chip between the circuitry and source for detecting said particle emissions. In one embodiment of the present invention, the source comprises a solder ball that is formed on a surface of the IC chip, and the solder ball is capable of emitting alpha-particles. The particle emissions detector of the present invention is a reverse biased Schottky diode. The IC chip is formed by (a) providing an IC chip having at least one layer of particle sensitive circuitry formed therein; (b) forming another layer having at least one particle sensor region situated therein on a surface of said IC chip; and (c) optionally, forming at least one particle emission source over said another layer.

On chip alpha-particle detector

Growing community of inventors

Charlotte, VT, United States of America

Wilbur David Pricer