Texas Instruments Corporation

Wilbur Christian Vogley

Karl M Guttag

Roger D Norwood

Duy-Loan T Le

Steven D Krueger

Anthony M Balistreri

Kenneth A Poteet

Joseph H Neal

Joseph P Hartigan

Jonathan H Shiell

Robert L Ward

An integrated circuit device test arrangement includes a plurality of microcomputers. Each of the microcomputers is interconnected directly through a separate test socket to a separate integrated circuit device that is inserted into the test socket. A device tester is coupled to the plurality of microcomputers for transmitting information between the device tester and the plurality of microcomputers. Each microcomputer contains instructions and data for performing a test routine on the associated integrated circuit device and transmitting selected results of the test routine to the tester.

Reduced cost, high speed integrated circuit test arrangement

Reduced cost, high speed circuit test arrangement

A synchronous dynamic random access memory (SDRAM) (,) is disclosed. The SDRAM (,) operates in synchronism with differential clock signals (CLK and /CLK). A timing and control circuit (,) compares the complementary differential clock signals (CLK and /CLK) to generate an internal clock signal (CLKI). By comparing the differential clock signals (CLK and /CLK) to generate the internal clock signal (CLKI), the preferred embodiment can compensate for degradations in the differential clock signals (CLK and /CLK). In addition, by utilizing the internal timing signal (CLKI) the preferred embodiment does not have to employ more complex circuits that must operate in synchronism with the edges of both differential clock signals (CLK and /CLK).

High-speed clock circuit for semiconductor memory device

A packet-based data storage system (,) includes a controller (,) and a number of packet-based data storage modules (,-,to,-n). The data storage modules (,-,to,-n) receive command/address information and a command clock on module command links (,-,to,-n) and provide access to storage locations by way of module data links (,-,to,-n). The controller (,) issues command/address information and a command clock signal on a controller command link (,). Data is passed to and from the controller (,) by a controller data link (,). Load protection is provided to the controller (,) and the storage modules (,-,to,-n) by command re-drive circuits (,-,to,-n), coupled between the controller command link (,) and the module command links (,-,to,-n), and data re-drive circuits (,-,to,-n) coupled between the controller data link (,) and the module data links (,-,to,-n).

Synchronous data storage system having re-drive circuits for reduced signal line loading

A data processing system (,) including a synchronous random access memory (,) and a method for accessing the synchronous random access memory are disclosed. A digital processor (,) of the data processing system is coupled to a system clock circuit (,) that produces a system clock signal for controlling operation of the digital processor. Addressable storage cells within the synchronous random access memory are accessed in response to the system clock signal and an address select signal (ADS) to write data into the storage cells or read data out from the storage cells. Initial row and column addresses are latched into a row address buffer (,) and a column address buffer (,). The data are read out from the memory in an order corresponding to a control signal (WT) in synchronization with the system clock signal. The synchronous random access memory device may be fabricated as a dynamic storage device or as a static storage device.

Synchronous memory and data processing system having a programmable burst order

A data processing system (,) including a synchronous random access memory (,) and a method for accessing the synchronous random access memory are disclosed. A digital processor (,) of the data processing system is arranged with a system clock circuit (,) that produces a system clock signal for controlling operation of the digital processor. Addressable storage cells within the synchronous random access memory are accessed in response to the system clock signal and a single select signal such as an address select signal (ADS) to write data into the storage cells or read data out from the storage cells. The synchronous random access memory device may be fabricated as a dynamic storage device or as a static storage device.

Synchronous dynamic random access memory and data processing system using an address select signal

A synchronous memory (,), comprising a row address circuit (,) latches a row address signal in response to a system clock signal and a binary select signal. The row address circuit produces at least one row select signal. A column address circuit (,) latches an initial column address signal in response to the system clock signal and the binary select signal. The column address circuit produces a plurality of column select signals in synchronization with the system clock signal. A memory array (,) is arranged in rows and columns of memory cells. Each memory cell stores a respective data bit. The memory array simultaneously produces an integral multiple of M data bits in response to the row select signal and the plurality of column select signals. An output circuit (OMUX) is coupled to receive the system clock signal and the integral multiple of M data bits. The output circuit produces a first data bit from a first group of M data bits on a bus (,) having M leads at a first time and a second data bit from a second group of M data bits on the bus having M leads at a second time after the first time in response to the system clock signal.

Data processing system having a synchronous memory with an output circuit which selectively outputs groups of M data bits

A data processing system (,) including a synchronous random access memory (,) and a method for accessing the synchronous random access memory are disclosed. A digital processor (,) of the data processing system is coupled to with a system clock circuit (,) that produces a system clock signal for controlling operation of the digital processor. Addressable storage cells within the synchronous random access memory are accessed in response to the system clock signal and an address select signal (ADS) to write data into the storage cells or read data out from the storage cells. Initial row and column addresses are latched into a row address buffer (,) and a column address buffer (,). A number of data bits corresponding to a control signal such as a wrap length (WL) signal are read out from the memory in synchronization with the system clock signal. The synchronous random access memory device may be fabricated as a dynamic storage device or as a static storage device.

Synchronous memory and data processing system having a programmable burst length

An integrated circuit device test arrangement includes a plurality of microcomputers. Each of the microcomputers is interconnected directly through a separate test socket to a separate integrated circuit device that is inserted into the test socket. A device tester is called to the plurality of microcomputers for transmitting information between the device tester and the plurality of microcomputers. Each microcomputer contains instructions and data for performing a test routine on the associated integrated circuit device and transmitting selected results of the test routine to the tester.

Test system and process with a microcomputer at each test location

A synchronous random access memory is arranged to be responsive directly to a system clock signal for operating synchronously with the associated microprocessor. The synchronous random access memory is further arranged to either write-in or read out data in a synchronous burst operation or synchronous wrap operation in addition to synchronous random access operations. The synchronous random access memory device may be fabricated as a dynamic storage device or as a static storage device.

High-speed memory arranged for operating synchronously with a

An active integrated circuit socket includes plural pin sockets receiving corresponding pins of an integrated circuit and plural socket pins making electrical contact with a printed circuit board. At least one active electronic component requiring electrical power for operation connects a pin sockets to a corresponding socket pin. The active electronic component may be a single ended input to differential output driver, a differential input to single ended output driver, a single ended to differential input/output transceiver or a voltage level shifter. These active components may include passive termination resistors. The single ended to differential transceiver may further include an enable input determining the direction of data transmission. This invention may be employed as an electronic system upgrade product including at least two active integrated circuit sockets connected via a flexible sheet including a plurality of electrical conductors connecting differential signal lines. The flexible sheet may dispose a grounded conductor between each pair of differential signal conductors. The differential signals on the printed circuit board or the flexible sheet enabled by this invention are better able to support high speed data transfer than the single ended signals at the pins of the integrated circuits.

High speed integrated circuit interconnection having proximally located

According to one aspect of the present invention, a selectable integrated circuit assembly (10) is disclosed. The assembly includes a first plurality of terminals (20) for communicating information to and from an integrated circuit device and a second plurality of terminals (22) for receiving an assembly address. The assembly (10) also includes select logic (14) connected to receive the assembly address and operable to generate select signals based upon the assembly address. The select signals have a selected state and a not-selected state. A plurality of switches (18) are connected between the first plurality of terminals (20) and the integrated circuit device. The plurality of switches (18) are connected to receive the select signals. The switches (18) operate, when the select signals are in the selected state, to connect the first plurality of terminals (20) to the integrated circuit device. When the select signals are in the non-selected state, the switches (18) operate to disconnect the first plurality of terminals (20) from the integrated circuit device. According to one embodiment of the present invention, the assembly is a selectable memory module (10).

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Missouri City, TX, United States of America

Wilbur Christian Vogley