Nxp B.v.

Koninklijke Philips Corporation N.v.

Trixell

Interuniversitair Micro-elektronica Centrum Vzw

Wibo Daniel Van Noort

Philippe Meunier-Beillard

Johannes Donkers

Erwin Hijzen

Jan Sonsky

Francois Neuilly

Celine Juliette Detcheverry

Andreas M Piontek

Ronald Dekker

Theodore James Letavic

Peter Deixler

Franciscus Petrus Widdershoven

Radu Surdeanu

Anco Heringa

Johannes J T M Donkers

Sebastien Nuttinck

Stefaan Van Huylenbroeck

Lis Karen Nanver

Antonius Lucien Adrianus Maria Kemmeren

Joost Melai

Erik Jan Lous

Ramon Jacob Havens

Petrus H C Magnee

Francis Zaato

Li Jen Choi

Wilhelmus Cornelis Maria Peters

Erwin Hujzen

Peter Magnee

Jan Zonsky

Eyup Aksen

Andreas Bernardus Maria Jansman

Godefridus Andrianus Maria Hurkx

Joost Willem Christiaan Veltkamp

An integrated circuit is provided, which comprises at least one first group each having at least one analog unit; and at least one second group each having at least one electronically settable semi-permanent switching unit coupled to the at least analog unit of the first group for trimming the first group and having at least one many-times-programmable and non-volatile cell (MTP). Each many-times-programmable cell (MTP) comprises at least one MOS transistor having a floating gate (FG) with a tunnel oxide (TO) and a first capacitor coupled to the floating gate (FG). The capacitance of the first capacitor is substantially larger than a gate-channel capacitance of the MOS transistor.

Integrated circuit with trimming

The invention provides a semiconductor device () for radiation detection, which comprises a substrate region () of a substrate semiconductor material, such as silicon, and a detection region () at a surface of the semiconductor device (), in which detection region () charge carriers of a first conductivity type, such as electrons, are generated and detected upon incidence of electromagnetic radiation (L) on the semiconductor device (). The semiconductor device () further comprises a barrier region () of a barrier semiconductor material or an isolation material, which barrier region () is an obstacle between the substrate region () and the detection region () for charge carriers that are generated in the substrate region () by penetration of ionizing radiation (X), such as X-rays, into the substrate region (). This way the invention provides a semiconductor device () for radiation detection in which the influence on the performance of the semiconductor device () of ionizing radiation (X), such as X-rays, that penetrates into the substrate region () is reduced.

Semiconductor device for radiation detection

The present invention provides a semiconductor device comprising a plurality of layers, the semiconductor device comprising:&#x2014;a substrate having a first major surface,&#x2014;an inductive element fabricated on the first major surface of the substrate, the inductive element comprising at least one conductive line, and&#x2014;a plurality of tilling structures in at least one layer, wherein the plurality of tilling structures are electrically connected together and are arranged in a geometrical pattern so as to substantially inhibit an inducement of an image current in the tilling structures by a current in the inductive element. It is an advantage of the above semiconductor device that, by using such tilling structures, an inductive element with improved quality factor is obtained. The present invention also provides a method for providing an inductive element in a semiconductor device comprising a plurality of layers.

Inductive and capacitive elements for semiconductor technologies with minimum pattern density requirements

The invention relates to a semiconductor device () with a substrate () and a semiconductor body () comprising a bipolar transistor with in that order a collector region (), a base region (), and an emitter region (), wherein the semiconductor body comprises a projecting mesa () comprising at least a portion of the collector region () and the base region (), which mesa is surrounded by an isolation region (). According to the invention, the semiconductor device () also comprises a field effect transistor with a source region, a drain region, an interposed channel region, a superimposed gate dielectric (), and a gate region (), which gate region () forms a highest part of the field effect transistor, and the height of the mesa () is greater than the height of the gate region (). This device can be manufactured inexpensively and easily by a method according to the invention, and the bipolar transistor can have excellent high-frequency characteristics.

Semiconductor device and method of manufacturing such a device

Electrically isolated, deep trench isolation (DTI) structures, are formed in a wafer, and a portion of the DTI structures are converted to electrically connected structures to provide a shielding function, or to provide connection to deep buried layers. In one aspect, DTI structures include a polysilicon filling over a liner layer disposed on the inner surface of a deep trench, the polysilicon is removed by isotropic etching, and the deep trench is re-filled with a conductive material. Alternatively, the polysilicon filling remains and a contact is formed to provide an electrical connection to the polysilicon. In another aspect, a deep trench is disposed in the wafer such that a lower portion thereof is located within a deep buried layer, and after the polysilicon is removed, an anisotropic etch removes a portion of the deep trench liner from the bottom of the deep trench, thereby allowing a tungsten deposition to make electrical contact with the deep buried layer.

Contacting and filling deep-trench-isolation with tungsten

The invention relates to a semiconductor device () comprising a semiconductor body () with a high-ohmic semi-conductor substrate () which is covered with a dielectric layer () containing charges, on which dielectric layer one or more passive electronic components () comprising conductor tracks () are provided, wherein, at the location of the passive elements (), a region () is present at the interface between the semiconductor substrate () and the dielectric layer (), as a result of which the conductivity of an electrically conducting channel induced in the device () by the charges is limited at the location of the region (). According to the invention, the region () is formed by deposition and comprises a semi-insulating material. As a result, the device () has a very low high-frequency power loss because the inversion channel is formed in the semi-insulating region (). The device () further allows for a higher temperature budget and hence for the integration of active semiconductor elements () into the semiconductor body (). A very suitable semi-insulating material for the region () is SiC, SIPOS or POLYDOX.

Semiconductors device and method of manufacturing such a device

The invention relates to a semiconductor device () with a substrate () and a semiconductor body () of silicon which comprises an active region (A) with a transistor (T) and a passive region (P) surrounding the active region (A) and which is provided with a buried conducting region () of a metallic material that is connected to a conductive region () of a metallic material sunken from the surface of the semiconductor body (), by which the buried conductive region () is made electrically connectable at the surface of the semiconductor body (). According to the invention, the buried conducting region () is made at the location of the active region (A) of the semiconductor body (). In this way, a very low buried resistance can be locally created in the active region (A) in the semiconductor body (), using a metallic material that has completely different crystallographic properties from the surrounding silicon. This is made possible by using a method according to the invention. Such a buried low resistance offers substantial advantages both for a bipolar transistor and for a MOS transistor.

Semiconductor device with low buried resistance and method of manufacturing such a device

The invention relates to a semiconductor device () with a substrate () and a semiconductor body () of silicon comprising a bipolar transistor with an emitter region, a base region and a collector region () first conductivity type, a second conductivity type opposite to said first conductivity type and the first conductivity type, respectively, with a first semiconductor region () comprising the collector region or the emitter region being formed in the semiconductor body (), on top of which a second semiconductor region () comprising the base region is present, on top of which a third semiconductor region () comprising the other of said collector region and said emitter region is present, said semiconductor body () being provided with a constriction at the location of the transition between the first and the second semiconductor region (), which constriction has been formed by means of an electrically insulating region () buried in the semiconductor body (). According to the invention a part of the semiconductor body that is formed above the buried electrically insulating region () is monocrystalline. This enables a strong lateral miniaturization of the device and results in excellent high frequency properties of the transistor. Such a device () is possible thanks to its manufacture with a method of manufacturing according to the invention.

Bipolar transistor having a second, base-comprising region consisting of a first layer, a second, constrictive, layer, and a third layer

A method of manufacturing a semiconductor device wherein a laminate structure comprising a sacrificial layer is sandwiched between two etch stop layers () and which separates a semiconductor membrane () from a bulk substrate () is used to provide an underetched structure. Access trenches () and support trenches () are formed in the layered structure through the thickness of the semiconductor layer () and through the upper etch stop layer (). The support trenches extend deeper through the sacrificial layer () and the lower etch stop layer and are filled. The sacrificial layer is exposed and etched away selectively to the etch stop layers to form a cavity () and realise a semiconductor membrane which is attached to the bulk substrate via a vertical support structure comprising the filled support trenches.

Methods relating to trench-based support structures for semiconductor devices

Consistent with an example embodiment, there is a bipolar transistor with a reduced collector series resistance integrated in a trench of a standard CMOS shallow trench isolation region. The bipolar transistor includes a collector region manufactured in one fabrication step, therefore having a shorter conductive path with a reduced collector series resistance, improving the high frequency performance of the bipolar transistor. The bipolar transistor further includes a base region with a first part on a selected portion of the collector region (), which is on the bottom of the trench, and an emitter region on a selected portion of the first part of the base region. A base contact electrically contacts the base region on a second part of the base region, which is on an insulating region. The collector region is electrically contacted on top of a protrusion with a collector contact.

Bipolar transistor and method of fabricating the same

The illumination system has a light source () with a plurality of light emitters (R, G, B). The light emitters comprise at least a first light-emitting diode of a first primary color and at least a second light-emitting diode of a second primary color, the first and the second primary colors being distinct from each other. The illumination system has a facetted light-collimator () for collimating light emitted by the light emitters. The facetted lightcollimator is arranged along a longitudinal axis () of the illumination system. Light propagation in the facetted light-collimator is based on total internal reflection or on reflection at a reflective coating provided on the facets of the facetted light-collimator. The facetted light-collimator merges into a facetted light-reflector () at a side facing away from the light source. The illumination system further comprises a light-shaping diffuser (). The illumination system emits light with a uniform spatial and spatio-angular color distribution.

Self-aligned epitaxially grown bipolar transistor

The invention relates to a method of manufacturing a bipolar transistor on a semiconductor substrate () which is provided with a first, a second and a third layer () of a first, second and third semiconductor material respectively, all of a first conductivity type. A first portion of the second layer () is transformed into a buried isolation region () comprising a first electrically insulating material. A first semiconductor region () of the first conductivity type, comprising, for example, a collector region, is formed from a second portion of the second layer () adjoining the buried isolation region () and a portion of the first layer () adjoining the second portion of the second layer (). Then a base region () is formed on the buried isolation region () and on the first semiconductor region () by transforming the third layer () into a second conductivity type, which is opposite to the first conductivity type. Thereafter a second semiconductor region () of the first conductivity type, comprising, for example, an emitter region, is formed on a part of the base region (). This method provides for the formation of a bipolar transistor with an advantageous decrease of the extrinsic collector to base region () capacitance by the fact that the value of this capacitance is mainly determined by the buried isolation region () which has a substantially lower dielectric constant than that of the collector to base region () junction.

Method of manufacturing a bipolar transistor

The invention provides a method of fabricating an extremely short-length dual-gate FET, using conventional semi-conductor processing techniques, with extremely small and reproducible fins with a pitch and a width that are both smaller than can be obtained with photolithographic techniques. On a protrusion () on a substrate (), a first layer () and a second layer () are formed, after which the top surface of the protrusion () is exposed. A portion of the first layer () is selectively removed relative to the protrusion () and the second layer (), thereby creating a fin () and a trench (). Also a method is presented to form a plurality of fins () and trenches (). The dual-gate FET is created by forming a gate electrode () in the trench(es) () and a source and drain region. Further a method is presented to fabricate an extremely short-length asymmetric dual-gate FET with two gate electrodes that can be biased separately.

Method of fabricating a dual gate FET

The invention relates to a semiconductor device () with a semiconductor body () comprising a high-ohmic semiconductor substrate () which is covered with a dielectric layer () containing charges, on which dielectric layer one or more passive electronic components () comprising conductor tracks () are present, and at the location of the passive elements () a semiconductor region () is present at the interface between the semiconductor substrate () and the dielectric layer (), a first conductivity-type conducting channel induced in the semiconductor substrate () by the charges being interrupted by, and at the location of, the semiconductor region (). According to the invention, the semiconductor region () is monocrystalline and of a second conductivity type, opposite to the first conductivity type. In this way the charge of an induced channel is locally compensated by the charge of the semiconductor regions (). The device () has a very low high-frequency power loss, because the inversion channel is interrupted at the location of the semiconductor region (). The device () further allows for a higher thermal budget and thus for the integration of active semiconductor elements () into the semiconductor body (). Preferably, the semiconductor region () comprises a large number of strip-shaped sub-regions (A,B,C).

The invention relates to a method of manufacturing a semiconductor device comprising a substrate () and a semiconductor body () in which at least one semiconductor element is formed, wherein, in the semiconductor body (), a semiconductor island () is formed by forming a first cavity () in the surface of the semiconductor body (), the walls of said first cavity being covered with a first dielectric layer (), after which, by means of underetching through the bottom of the cavity (), a lateral part of the semiconductor body () is removed, thereby forming a cavity () in the semiconductor body () above which the semiconductor island () is formed, and wherein a second cavity () is formed in the surface of the semiconductor body (), the walls of said second cavity being covered with a second dielectric layer, and one of the walls covered with said second dielectric layer forming a side wall of the semiconductor island (). According to the invention, the same dielectric layer () is chosen for the first and the second dielectric layer, a lateral size of the second cavity () and the thickness of the dielectric layer () are chosen such that the second cavity () becomes nearly completely filled by the dielectric layer (), and the lateral sizes of the first cavity () are chosen such that the walls and the bottom of the first cavity () are provided with a uniform coating by the dielectric layer (). In this way, a semiconductor island () which is isolated from its environment can be made using a minimum number of (masking) steps.

Growing community of inventors

Wappingers Falls, NY, United States of America

Wibo Daniel Van Noort