Intel Corporation

Whitney Michael Bryks

Brandon C Marin

Dilan Seneviratne

Praneeth Kumar Akkinepally

Frank Truong

Sarah Blythe

Yosef Kornbluth

Bainye Francoise Angoua

Joshua Stacey

Srinivas V Pietambaram

Robert Alan May

Nasser A Kurd

Tarek A Ibrahim

Siddharth K Alur

Mohamed A Abdelmoneum

Brent R Carlton

Sri Chaitra J Chavali

Jason M Gamba

Eduardo Alban

Jason A Mix

Srinivas Venkata Ramanuja Pietambaram

Jieying Kong

Ravindranadh T Eluri

Ala Omer

Chelsea M Groves

Peumie Abeyratne Kuragama

Sarah Shahraini

Junxin Wang

Aaditya Anand Candadai

Embodiments described herein may be related to apparatuses, processes, and techniques directed an optical waveguide formed in a glass layer. The optical waveguide may be formed by creating a first trench extending from a surface of the glass layer, and then creating a second trench extending from the bottom of the first trench, then subsequently filling the trenches with a core material which may then be topped with a cladding material. Other embodiments may be described and/or claimed.

Optical waveguide formed within in a glass layer

An electronic device and associated methods are disclosed. In one example, the electronic device includes a MEMS die located within a substrate, and below a processor die. In selected examples, the MEMS die includes a resonator. Example methods of forming MEMS resonator devices are also shown.

Integrated MEMS resonator and method

The present disclosure is directed to a carrier chuck having a base plate with a top surface, a plurality of first magnets positioned in a first region of the top surface, the plurality of first magnets configured to produce a first electromagnetic field to retain or suspend a panel placed on the carrier chuck during panel processing, wherein the first region corresponds to a region of the panel which comprises a magnetic material.

Carrier chuck comprising a plurality of magnets and methods of forming and using thereof

An electronic substrate may be formed having at least one dielectric layer that is heterogeneous. The heterogeneous dielectric layer may comprise three separately formed materials that decouple the critical regions within a dielectric layer and allow for the optimization of desired interfacial properties, while minimizing the impact to the bulk requirements of the electronic substrate.

Electronic substrates having heterogeneous dielectric layers

The present disclosure is directed to a position-controlled lamination tool or press that includes an array or plurality of pressure sensors and an array or plurality of heating/cooling elements or components, which may be coupled together, for preventing or reducing laminating film or material bleed out and improving thickness variation performance. The pressure sensors may provide a controller, which is coupled to the lamination tool, with real-time feedback on any thickness variations across a substrate panel and the controller may adjust the temperature output of the heating and cooling elements to locally modify the viscosity of the laminating material in one or more regions of the substrate panel to either decrease or increase the flowability of the laminating material.

Dry film lamination with dynamic feedback control

A package substrate may include a build-up layer. The build-up layer may include a dielectric material and one or more microspheres. The one or more microspheres may include a magnetic core that includes a first material that is a first oxidation-resistant material. Further, the one or more microspheres may include a shell to encapsulate the core, and the shell may include a second material that is a second oxidation-resistant material. The package substrate may further include a metal layer coupled with the build-up layer.

Core-shell particles for magnetic packaging

A system is disclosed, which comprises a component carrier having a first side, and a second side opposite the first side; and a light source to couple light into the carrier. In an example, the carrier is to propagate, through internal reflection, at least a portion the light to both the first and second sides of the carrier. The portion of light may be sufficient to release a first component and second component affixed to the first and second sides of the carrier via a first photosensitive layer and second photosensitive layer, respectively.

Dual side de-bonding in component carriers using photoablation

Disclosed embodiments include in-recess fabricated vertical capacitor cells, that can be assembled as close to the surface of a semiconductor package substrate as the first-level interconnect surface. The in-recess fabricated vertical capacitor cells are semiconductor package-integrated capacitors. Disclosed embodiments include laminated vertical capacitor cells where a plated through-hole is twice breached to form opposing capacitor plates. The breached, plated through-hole capacitors are semiconductor package-integrated capacitors.

Package-integrated vertical capacitors and methods of assembling same

Semiconductor package substrates and methods of forming semiconductor package substrates are described. In an example, a semiconductor package substrate includes an interfacial layer between a metal layer and a dielectric layer. For example, the interfacial layer may be attached to the metal layer and the dielectric layer by a chemical bond, e.g., a coordinate bond or a covalent bond. Accordingly, the metal layer may adhere to the dielectric layer.

Semiconductor package substrate having an interfacial layer

Embodiments of the present disclosure describe an integrated circuit and associated fabrication techniques and configurations, which may include forming on at least one of a metal layer or a polymer layer of an integrated circuit die a surface layer that includes an adhesion-functional group, and applying to the surface layer a next layer to adhere to the surface layer with the adhesion-functional group. In embodiments wherein the at least one of the metal layer or the polymer layer is a polymer layer, forming the surface layer may include copolymerizing on the polymer layer a polar monomer that includes the adhesion-functional group. In embodiments wherein the at least one of the metal layer or the polymer layer is a metal layer, forming the surface layer may include forming on the metal layer a self-assembled monolayer that includes amine group terminations. Other embodiments may be described and/or claimed.

Integrated circuit surface layer with adhesion-functional group

Growing community of inventors

San Diego, CA, United States of America

Whitney Michael Bryks