Cisco Technology, Inc.

Lsi Logic Corporation

Wheling Cheng

Sergio D Camerlo

Roger Antoine Karam

Aritharan Thurairajaratnam

Ashwath Nagaraj

Scott L Kirkman

Bangalore J Shanker

Suryaprakash Jonnavithula

A method of fabricating a printed circuit board having a coaxial via is disclosed. The method includes assembling a plurality of layers configured in a stack so that the plurality of layers has a top signal layer and a bottom signal layer; forming a hollow via through the plurality of layers to connect GND layers in the printed circuit board, forming or inserting into the hollow via a conductor coated with non-conductive material, covering the top layer and bottom layer with dielectric and patterned signal layers, covering the top layer and bottom layer with a masking agent, plating the top layer and bottom layer with a conductive material that connects signal traces within via, and removing the masking agent from the top layer and bottom layer.

Method for fabricating a printed circuit board having a coaxial via

In a System-in-Package (SiP) module, a method and a system for optimizing the timing margin of source-synchronous interface clocks is provided. Clock signals generated by first device are transmitted to serpentine traces located on a Printed Circuit Board (PCB) which adjusts the active edge of one signal relative to another signal. The serpentine trace introduces a delay in the clock signal thereby optimizing timing margins. By providing access to signals otherwise internal the SiP, testing and signal verification is also simplified.

Method and system to optimize timing margin in a system in package module

A method of fabricating a printed circuit board having a coaxial via, includes. The method includes assembling a plurality of layers configured in a stack so that the plurality of layers has a top signal layer and a bottom signal layer; forming a hollow via through the plurality of layers to connect GND layers in the printed circuit board, forming or inserting into the hollow via a conductor coated with non-conductive material, covering the top layer and bottom layer with dielectric and patterned signal layers, covering the top layer and bottom layer with a masking agent, plating the top layer and bottom layer with a conductive material that connects signal traces within via, and removing the masking agent from the top layer and bottom layer.

A surface mount adaptor allows for removable attachment of debugging connectors to a circuit board and provides high density access to the circuit board under test at a single location. A circuit board testing assembly has a support member having debugging connectors coupled to a first surface of the support member, the debugging connectors being configured to attach to a circuit board testing device. The circuit board testing assembly also has a support member connector coupled to a second surface of the support member and in electrical communication with the debugging connectors. The support member is configured to removably attach to a circuit board connector surface mounted to a first surface of a circuit board. Removable attachment of the debugging connectors from the circuit board provides an availability of space on the top side of the circuit board for additional circuit board components and traces.

Methods and apparatus for testing a circuit board using a surface mountable adaptor

Disclosed is a pair of conductive rings and method for making the conductive rings for introducing an integral network of capacitive structures around a semiconductor die of a semiconductor package. The pair of conductive rings include a ground rail ring that is defined around a semiconductor die pad that is configured to receive a semiconductor die. The ground rail ring has a first plurality of extension spokes that extend away from the ground rail ring. The pair of conductive rings further includes a power rail ring that is defined around the semiconductor die pad. The power rail ring has a second plurality of extension spokes that extend away from the power rail ring and toward the ground rail ring.

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Palo Alto, CA, United States of America

Wheling Cheng