International Business Machines Corporation

Westerfield John Ficken

Hayden C Cranford, Jr

Joseph M Stevens

Hayden Cranford

Daniel P Greenberg

Louis L Hsu

Louis Lu-Chen Hsu

James Stephen Mason

Minhan Chen

Steven John Zier

David A Freitas

Wentai Liu

Paul Alan Owczarski

Phil J Murfet

A test circuit for a serial link receiver includes a first current source coupled to a first input of the serial link receiver, and a second current source coupled to a second input of the serial link receiver. The first current source is symmetrically matched to the second current source. A first switch of the first current source is turned on to permit a charge-retaining mechanism thereof to be charged. A second switch of the first current source is turned on to permit the retained charge retained to be asserted on the first input. The charge turns on a control switch of the first current source, through which the charge is asserted on the first input. A charge-draining mechanism of the first current source is turned on to thereafter permit the charge to be drained in a controlled manner after the charge has been asserted.

Test circuit for serial link receiver

Embodiments include a time-sharing detector that is designed to enable comparison of a first reference voltage and a second reference voltage against the serial data transmission in a specified pattern. In many embodiments, the pattern is pre-defined and, in some embodiments, the pattern includes an overlap period. During the overlap period both the first and the second reference voltages are compared with the data transmission to determine if valid data can be detected. Upon detecting a valid bit based upon one of the reference voltages, an output signal is generated to indicate that the data transmission includes a valid data signal. Advantageously, alternating between the comparisons can reduce power consumption. In many embodiments, the power reduction can be, for example, 50%, depending upon the specified pattern.

Reducing power consumption in signal detection

Methods, systems, and media to time-share the signal detection between reference voltages for a data transmission are contemplated. Embodiments include a time-sharing detector that is designed to enable comparison of a first reference voltage and a second reference voltage against the serial data transmission in a specified pattern. In many embodiments, the pattern is pre-defined and, in some embodiments, the pattern includes an overlap period. During the overlap period both the first and the second reference voltages are compared with the data transmission to determine if valid data can be detected. Upon detecting a valid bit based upon one of the reference voltages, an output signal is generated to indicate that the data transmission includes a valid data signal. Advantageously, alternating between the comparisons can reduce power consumption. In many embodiments, the power reduction can be, for example, 50%, depending upon the specified pattern.

A circuit device and method for designing a serial link receiver, which accommodates a wide input voltage range and provides tolerance to high termination voltages. The receiver is designed with a pair of RC networks connected inline between the input and the preamplifier and a common mode feedback loop, which monitors shifts in the common mode voltage and adjusts the inputs provided to the preamplifier. The circuit device maintains a flat bandwidth to accommodate all signaling rates.

Serial link receiver with wide input voltage range and tolerance to high power voltage supply

A system and method for a predriver and driver interface having scalable output drive capability with corresponding scalable power is disclosed. The system includes a predriver to driver interface having a data source; a plurality of predrivers, each coupled to the data source and responsive to an enable signal, for driving a predriven data signal only when a corresponding enable signal is asserted and for consuming reduced power when the corresponding enable signal is deasserted; a plurality of drivers, each coupled to one of the plurality of predrivers to receive a corresponding predriven data signal from the corresponding predriver and responsive to the enable signal coupled to the corresponding predriver, for driving an output with the predriven data signal only when the corresponding enable signal is asserted and for consuming reduced power when the corresponding enable signal is deasserted; and a controller, coupled to the predrivers and the drivers, for selectively asserting the enable signals to provide variable output drive capability of the data source to the output while providing scalable power consumption.

Method and system for scalable pre-driver to driver interface

A method and system for is disclosed for reducing intersymbol interference in a stream of data bits to be transmitted over a transmission medium. Aspects of the present invention include a phase delayed clock generated from a reference clock that produces an edge on sub-bit boundaries; and a digital filter coupled to the phase delayed clock for performing equalization on the data bits, wherein the phase delayed clock causes the digital filter to perform partial clock switching, such that equalization is performed on the data bits on-sub-bit boundaries.

Equalizer for reduced intersymbol interference via partial clock switching

Offset voltages in differential amplifiers are minimized by controlling compensation currents through the load impedances of the amplifiers. The currents are varied while sensing the polarity of the offset voltage. When the polarity changes, the current values are latched to keep the offset voltage at a minimum.

Differential amplifier offset voltage minimization independently from common mode voltage adjustment

A system and method is disclosed that efficiently provides standard termination blocks in an approved cell library that are flexible and customizable. A serial communications system includes a transmitter for sending a serial data signal at an output of the transmitter; a transmitter terminator, coupled to the output and responsive to a first configuration signal, to variably terminate a first selected property of the output; a receiver for processing the serial data signal at an input of the receiver, the input of the receiver coupled to the output of the transmitter; and a receiver terminator, coupled to the input of the receiver and responsive to a second configuration signal to variably terminate a second selected properly of the input. The method for operating a serial communications system includes the steps of: (a) providing a plurality of unidirectional serial links, each of the links between a transmitter and a receiver, an output of each transmitter coupled to an input of a corresponding receiver by a medium type with each output having a transmitter terminator and each input having a receiver terminator; (b) terminating variably a selected property of the output of each transmitter to match the medium type coupling the output to the input of the corresponding receiver by use of a transmitter termination configuration signal asserted to the transmitter; and (c) terminating variably a selected property of the input of each receiver to match the medium type coupling the input to the output of the corresponding transmitter by use of a receiver termination configuration signal asserted to the receiver.

Method and system for configuring terminators in a serial communication system

An apparatus and method is provided for detecting loss of differential signal carried by a pair of differential signal lines. According to the method, a common mode level is detected from voltages on the pair of differential signal lines. A threshold level is generated, referenced to the detected common mode level. A signal level is generated from the voltages on the pair of differential signal lines, the signal level being averaged over a first period of time. From the threshold level and the detected common mode level a reference level is generated, the reference level being averaged over a second period of time longer than then the first period of time. The signal level is compared to the reference level to determine if a signal is present on the pair of differential signal lines.

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Cary, NC, United States of America

Westerfield John Ficken