Micron Technology Incorporated

Intel Corporatino

Wesley O McKinsey

Anilkumar Chandolu

Christopher J Larsen

Tom Jibu John

Prakash Rau Mokhna Rau

S M Istiaque Hossain

Arun Kumar Dhayalan

Jun Liu

Gordon A Haller

Hongbin Zhu

Fei Wang

Yiping Wang

Wei Yeeng Ng

Jun Zhao

Jeremy F Adams

Mark A Levan

Zhiqiang Xie

Methods, systems, and devices for plasma-doped trenches for memory are described. A method for forming a memory device with plasma-doped trenches may include forming a stack of materials having alternating layers of polysilicon and oxide materials. A trench may be etched in the stack and doped using a plasma doping process. In some examples, the trench may be doped by applying Boron fluoride, diborane, methane, or Boron and Carbon Hydride gases diluted with Hydrogen (H) or Helium to the sidewalls and bottom surface of the trench, which may dope portions of the polysilicon material with Boron, Carbon, Fluorine, Helium, or Hydrogen.

Plasma-doped trenches for memory

An electronic device comprising a lower deck and an upper deck adjacent to a source. Each of the lower deck and the upper deck comprise tiers of alternating conductive materials and dielectric materials. Each of the lower deck and the upper deck also comprise an array region and one or more non-array regions. Memory pillars are in the lower deck and the upper deck of the array region and the memory pillars are configured to be operably coupled to the source. Dummy pillars are in the upper deck of the one or more non-array regions and the dummy pillars are configured to be electrically isolated from the source. Another conductive material is in the upper deck and the lower deck of the one or more non-array regions. Additional electronic devices and related systems and methods of forming an electronic device are also disclosed.

Electronic devices including pillars in array regions and non-array regions

Electronic devices including pillars in array regions and non-array regions, and related systems and methods

Conductive structure technology is disclosed. In one example, a conductive structure can include an interconnect and a plurality of conductive layers overlying the interconnect. Each conductive layer can be separated from an adjacent conductive layer by an insulative layer. In addition, the conductive structure can include a contact extending through the plurality of conductive layers to the interconnect. The contact can be electrically coupled to the interconnect and insulated from the plurality of conductive layers. Associated systems and methods are also disclosed.

Solid state memory device, and manufacturing method thereof

Growing community of inventors

Nampa, ID, United States of America

Wesley O McKinsey