Future Wei Technologies, Inc.

Oracle International Corporation

Oracle America, Inc.

Baidu USA LLC

Huawei Technologies Co., Limited

Wesley M Shao

Yong Colin Zou

Junwei Bao

Ji Li

Jinshui Liu

Mark Allan Kampe

Huawei Liu

Muhui Lin

Cameron Bahar

Govinda Tatti

Colin Yong Zou

Davy Huang

Thomas Boyle

Eric E Lowe

Weiyu Wendy Lu

Scott Michael Carter

Wendy Lu

Lijiang Li

Cheng Sean Ye

Zhijun Robin Fu

Jason Zeng

Vivek Surabhi

Chang Yu

Andrew Yao

Ligang Chen

An extended peripheral component interconnect express (PCIe) device includes a host PCIe fabric comprising a host root complex. The host PCIe fabric has a first set of bus numbers and a first memory mapped input/output (MMIO) space on a host CPU. An extended PCIe fabric includes a root complex endpoint (RCEP) as part of an endpoint of the host PCIe fabric. The extended PCIe fabric has a second set of bus numbers and a second MMIO space separate from the first set of bus numbers and the first MMIO space, respectively.

System and method for extended peripheral component interconnect express fabrics

An exemplary embodiment extended peripheral component interconnect express (PCIe) device includes a host PCIe fabric comprising a host root complex. The host PCIe fabric has a first set of bus numbers and a first memory mapped input/output (MMIO) space on a host CPU. An extended PCIe fabric includes a root complex endpoint (RCEP) as part of an endpoint of the host PCIe fabric. The extended PCIe fabric has a second set of bus numbers and a second MMIO space separate from the first set of bus numbers and the first MMIO space, respectively.

An apparatus includes a chassis housing a control server compartment, a compute server compartment, and an input and output (IO) subsystem compartment. The apparatus further includes an IO subsystem inserted into the IO subsystem compartment, a compute server inserted into the compute server compartment, and a control server inserted into the control server compartment coupled to the compute server via an Ethernet connection. The IO subsystem includes one or more IO modules, where at least some of the IO modules can be coupled to sensors. The compute server receives the sensor data from the IO subsystem via some PCIe links and generates planning and control data based on the sensor data for controlling the autonomous vehicle. The control server controls and operates the autonomous vehicle by sending control commands to hardware of the autonomous vehicle based on the planning and control data received from the compute server.

Apparatus for controlling and operating an autonomous vehicle

A method for operating a device adapted to store information with high reliability includes determining a storage address for a data payload portion of a write request in accordance with a configuration of a communications interface coupled to the device, where the data payload is to be stored in mirroring groups of cache storage partitions of a plurality of cache storage modules. The method also includes generating a payload read request in accordance with the storage address, and prompting the communications interface to initiate the storing of the data payload, in parallel, in the mirroring groups in accordance with the payload read request.

System and method for reliably persisting storage writes at high speed

In one embodiment, a dedicated time processing device inserted into a peripheral bus coupling or embedded with at least some of the rest of system components (e.g., processor, memory) of a data processing system to synchronize a system clock of the data processing system. The peripheral bus can be a Peripheral Component Interface (PCI) bus, a PCI Express (PCIe) link, a PCI extended (PCI-X) bus, or the like. The time processing device receives high precision time from a high precision time source, such as global positioning system (GPS) time source. The time processing device decodes and processes the received time and stores the time in an internal time register. The time processing device further includes an interface to allow an external component (e.g., a processor) to retrieve with low latency the time stored in the time register for the purpose of synchronizing the system clock.

Method and system for high precision time synchronization

An IO subsystem chassis includes IO modules and IO slots to receive the IO modules inserted from a frontend of a housing, a baseboard disposed within the housing, the baseboard including first connectors corresponding to the IO slots to receive and connect the IO modules. Each of the IO modules can be coupled a server via the backend panel using a cable. Each IO module includes an IO card having a peripheral device mounted thereon and a card holder having a first receiving socket to receive and hold the IO card plugged in vertically and downwardly. The card holder further includes a second connector to engage with or disengage from a corresponding one of the first connectors of the baseboard horizontally, when the IO module is inserted into or removed from a corresponding IO slot from the frontend, without having to removing the housing.

Hot-plug capable input and output (IO) subsystem

A method for accessing a device in a primary peripheral component interconnect express (PCIe) domain from a secondary PCIe domain includes determining which one or more virtual functions of the device in the primary PCIe domain are to be made available to the secondary PCIe domain. A virtual function driver is installed in the primary PCIe domain associated with the one or more virtual functions. Information corresponding to the one or more virtual functions is provided to the secondary PCIe domain. A virtual function driver associated with the one or more virtual functions is installed in the secondary PCIe domain from the information. The virtual function driver in the secondary PCIe domain has same properties as the virtual function driver in the primary PCIe domain. The device in the primary PCIe domain is accessed from the virtual function driver in the secondary PCIe domain.

Method to use PCIe device resources by using unmodified PCIe device drivers on CPUs in a PCIe fabric with commodity PCI switches

A method for extending a Peripheral Component Interconnect Express (PCIe) domain. A configuration space address can be allocated to a PCIe device in an extended domain from a memory address of a root complex endpoint device, a correspondence between the configuration space address and a bus number/device number/function number (BDF) can be established, and a bus number can be allocated from a second bus set of the extended domain to a PCIe device discovered in the extended domain, where the bus number is used for determining the BDF of the PCIe device discovered in the extended domain, so as to access, according to the correspondence between the configuration space address and the BDF and by using the BDF of the PCIe device discovered in the extended domain, a configuration space register of the PCIe device discovered in the extended domain.

Method and apparatus for extending PCIe domain

Per-Function Downstream Port Containment (pF-DPC) is an extension to Downstream Port Containment (DPC) in the Peripheral Component Interconnect express (PCIe) standard. Pf-DPC confines non-fatal errors to specific functions of an end-point device without disabling the link between a PCIe port and the end-point device. PCIe ports configured for pF-DPC may filter (e.g., drop) packets carrying routing identifiers (RIDs) and/or addresses assigned to a function affected by a non-fatal error, while continuing to forward packets carrying RIDs/addresses associated with remaining operable functions over the corresponding link.

Per-function downstream port containment

Growing community of inventors

Menlo Park, CA, United States of America

Wesley M Shao