Silicon Space Technology Corporation

Wesley H Morris

Rex Everett Lowther

David R Gifford

William H Speece

Glenn A Dejong

Jack E Clark, Ii

Richard D Cherne

Richard L Lichtel

An example integrated circuit includes a first memory array including a first plurality of data groups, each such data group including a respective plurality of data bits. The integrated circuit also includes a first error detection and correction (EDAC) circuit configured to detect and correct an error in a data group read from the first memory array. The integrated circuit also includes a first scrub circuit configured to access in a sequence each of the first plurality of data groups to correct any detected errors therein. Both the first EDAC circuit and the first scrub circuit include spatially redundant circuitry. The first EDAC circuit and the first scrub circuit may include buried guard ring (BGR) structures, and may include parasitic isolation device (PID) structures. The spatially redundant circuitry may include dual interlocked storage cell (DICE) circuits, and may include temporal filtering circuitry.

Memory circuit incorporating radiation-hardened memory scrub engine

Semiconductor devices can be fabricated using conventional designs and process but including specialized structures to reduce or eliminate detrimental effects caused by various forms of radiation. Such semiconductor devices can include the one or more parasitic isolation devices and/or buried guard ring structures disclosed in the present application. The introduction of design and/or process steps to accommodate these novel structures is compatible with conventional CMOS fabrication processes, and can therefore be accomplished at relatively low cost and with relative simplicity.

Method and structure for radiation hardening a semiconductor device

Method for radiation hardening a semiconductor device

Semiconductor devices can be fabricated using conventional designs and process but including specialized structures to reduce or eliminate detrimental effects caused by various forms of radiation. Such semiconductor devices can include one or more parasitic isolation devices and/or buried layer structures disclosed in the present application. The introduction of design and/or process steps to accommodate these novel structures is compatible with conventional CMOS fabrication processes, and can therefore be accomplished at relatively low cost and with relative simplicity.

Radiation hardened isolation structures and fabrication methods

Fabrication methods for radiation hardened isolation structures

Methods for operating and fabricating a semiconductor device having a buried guard ring structure

Buried guard ring and radiation hardened isolation structures and fabrication methods

Buried guard ring structures and fabrication methods

An SOI/SOS thin film MOS mesa architecture has its body/channel region extended beyond the source and drain regions and the impurity concentration is increased at a selected portion (e.g. an end portion) of the extended body region, so as to provide both a body tie access location which enables the body/channel region to be terminated to a prescribed bias voltage (e.g. Vss), and a channel stop region that is effective to functionally interrupt a current leakage path or `parasitic` N-channel that may be induced along sidewall surface of the P-type material of the body/channel region. In another embodiment, ionizing radiation-induced inversion of the sidewalls of the P-type body/channel region is prevented by an asymmetric sidewall channel stop structure formed in opposite end portions of the source region.

SOI CMOS device having body extension for providing sidewall channel

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Austin, TX, United States of America

Wesley H Morris