International Business Machines Corporation

Wesley David Martin

Layne A Berge

Benjamin A Fox

George Russell Zettles, Iv

Gerald Keith Bartley

Richard Boyd Ericson

Trevor Joseph Timpane

David W Siljenberg

Benjamin W Mashak

Ay Vang

George Zettles

Matthew Stephen Doyle

Embodiments herein discuss tuning a testing apparatus to better match the input response of a target system in which a cable will be used. For example, conductors in the cable may have a different skew depending on the system in which they are used. The testing apparatus may be tuned using frequency information regarding the type of signals that will be driven on the cable when installed in the target system. In one embodiment, the testing apparatus adjusts a testing cycle refresh rate for generating a testing signal which changes the frequency content of the testing signal. Using the adjusted testing cycle refresh rate results in the driver outputting a testing signal that better reflects the actual signals that will be transmitted on the cable in the target system.

Tuning a testing apparatus for measuring skew

A system includes a transmit equalizer to equalize a data stream using a set of transmit parameters to generate an input signal. The system further includes a communication channel to receive the input signal. The system further includes a receive equalizer to receive an output signal from the communication channel in response to the input signal and detect the data stream from the output signal using a set of receive parameters. The system additionally includes a controller to change the set of transmit parameters in response to a condition, where the transmit parameters, the receive parameters, and the condition are selected to both enable the receive equalizer to detect the data stream from the output signal and reduce the likelihood of an external circuit detecting the data stream from the output signal.

Data security using high speed serial equalization

The embodiments of the present disclosure identify a target chip from among multiple chips coupled to a shared bus and customize an optimization parameter for the particular chip. Stated differently, in a communication system where only one chip (or a subset of chips) on a shared bus is the intended target, the system can customize an optimization parameter for the specific location of the target chip on the bus. As new data is received that is intended for a different chip&#x2014;i.e., the target chip changes&#x2014;the system can dynamically change the parameter based on the location of the new target chip on the bus.

Adjusting an optimization parameter to customize a signal eye for a target chip on a shared bus

Embodiments herein discuss tuning a testing apparatus to better match the input response of a target system in which a cable will be used. For example, conductors in the cable may have a different skew depending on the system in which they are used. The testing apparatus may be tuned using frequency information regarding the type of signals that will be driven on the cable when installed in the target system. In one embodiment, the testing apparatus uses the frequency information to configure a programmable clock source that can be used to shape a reference clock and control a driver to match the signals in the target system. Using the clock source to modify the reference clock results in the driver outputting a testing signal that better reflects the actual signals that will be transmitted on the cable in the target system.

Method and apparatus for clocked data eye measurement at synchronous interfaces is provided. A receiver may generate first vector information corresponding to data received on at least one communication channel at the receiver. The receiver may generate second information regarding when the data was latched by a clock signal, the clock signal being received on a separate communication channel at the receiver. The first vector information may be combined with the second information to generate combined information, the combined information indicating a quality of latching the data.

Method and apparatus for clocked data eye measurement

An apparatus includes a memory array to generate a data eye diagram. The memory array includes a plurality of rows of memory cells. The memory cells include a first row corresponding to a first sampling circuit of a first plurality of sampling circuits. The first sampling circuit is configured to compare an input voltage signal to a first reference voltage. The memory cells also include a second row corresponding to a second sampling circuit of the first plurality of sampling circuits. The second sampling circuit is configured to compare the input voltage signal to a second reference voltage. Each memory cell of the memory array is an incremental multi-bit counter.

Memory array to generate a data eye diagram

A method, system and computer program product are provided for implementing frequency spectrum analysis of noise in a device under test using causality (Hilbert Transform) results of Vector Network Analyzer (VNA) VNA-generated S-parameter model Information. A plurality of S-parameter samples are collected from the VNA generated S-parameter model Information. A Hilbert Transform of the collected plurality of S-parameter samples is used for error magnitude per frequency point analysis. An average error magnitude of predefined collected error magnitude samples is calculated to identify environmental noise in the device under test and used to identify acceptable environmental effects on the device under test.

Implementing frequency spectrum analysis using causality Hilbert Transform results of VNA-generated S-parameter model information

An apparatus and method for simulation and testing of electronic systems using a single model that has the composite behavioral information of multiple parts. The single model allows the designer to simulate using one model that captures the anticipated extremes (best case behavior to worst case behavior) across a collection of devices from different vendors.

Apparatus and method for composite behavioral modeling for multiple-sourced integrated circuits

A high frequency connector utilizes flex strip signal/reference conductor pairs extending in channels formed in a dielectric connector body between terminations at connector ends. The flex strips are formed as signal and reference conductor traces separated by a flexible dielectric wherein the impedance can be influenced by the width of the signal and reference traces and the thickness and selected material of the dielectric separating the adjoining conductor traces. Design of the flex strip assemblies is used to vary the capacitance which enables the connector impedance to match the impedance of the circuits and/or cables connected to the connector and mitigate any discontinuities among the sequence of circuit paths. The close proximity of signal and reference traces within the pair and the separation of signal lines in the connector body reduces cross talk by minimizing mutual inductance between signal lines.

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Elgin, MN, United States of America

Wesley David Martin