Intel Corporation

Wesley D McCullough

Rohit A Vidwans

Mark T Bohr

Wilfred Gomes

Joseph F Rohlman

Joel C Huang

Robert L Sankman

Ravindranath Vithal Mahajan

Rajesh Kumar

Nevine Nassif

Udi Sherel

Leonard M Neiberg

The present disclosure is directed to systems and methods of conductively coupling a plurality of relatively physically small core dies to a relatively physically larger base die using an electrical mesh network that is formed in whole or in part in, on, across, or about all or a portion of the base die. Electrical mesh networks beneficially permit the positioning of the cores in close proximity to support circuitry carried by the base die. The minimal separation between the core circuitry and the support circuitry advantageously improves communication bandwidth while reducing power consumption. Each of the cores may include functionally dedicated circuitry such as processor core circuitry, field programmable logic, memory, or graphics processing circuitry. The use of core dies beneficially and advantageously permits the use of a wide variety of cores, each having a common or similar interface to the electrical mesh network.

Distributed semiconductor die and package architecture

Systems and methods of providing redundant functionality in a semiconductor die and package are provided. A three-dimensional electrical mesh network conductively couples smaller semiconductor dies, each including circuitry to provide a first functionality, to a larger base die that includes circuitry to provide a redundant first functionality to the semiconductor die circuitry. The semiconductor die circuitry and the base die circuitry selectively conductively couple to a common conductive structure such that either the semiconductor die circuitry or the base die circuitry is able to provide the first functionality at the conductive structure. Driver circuitry may autonomously or manually, reversibly or irreversibly, cause the semiconductor die circuitry and the base die circuitry couple to the conductive structure. The redundant first functionality circuitry improves the operational flexibility and reliability of the semiconductor die and package.

Functionally redundant semiconductor dies and package

A mechanism and method for use in a superscalar microprocessor for storing into a register file within a single clock cycle, the results of multiple instructions (or micro-ops) that become available for storage into the register file at the same instant thus avoiding a microprocessor stall. The present invention may store, during a single clock cycle, results of up to four instructions that become available at the same time and that may target the same register, flag or portion thereof. By storing the results of the instructions (that are executed in parallel) at the same time, the present invention avoids inefficient stalls otherwise associated with prior art microprocessors when to or more instructions (or micro-ops) target the same register, register portion, or flag. The present invention utilizes a special decoder scheme, coupled with merge and priority logic to store the results into the real register file within a single clock cycle. Results of multiple instructions that may target the same register or the same register portion (i.e., data prioritizations are required) or results that target different portions of the same register (i.e., data merges are required) are supplied into the register file during one clock period. The same is true for explicit and implicit flag updates.

Having write merge and data override capability for a superscalar

A multi-port register contains a plurality of cells each capable of storing at least two states. The cells contain at least one read and one write port. Each read port contains a corresponding read enable line, a read data line, and a read transistor stack. Each write port contains a corresponding write enable line, write data line, and a write transistor stack. The read data line is coupled to a pre-charge circuit that charges the read data line to a pre-determined threshold level prior to reading the contents of the cell. The read transistor stack couples the output of the cell to the corresponding read data line such that the read data line is pulled to ground when the cell stores a first logic state, and the read data line retains the pre-determined voltage state when the cell stores the second logic state. The write transistor stack couples the write data line to the cell such that writing a first logic state on the write data line pulls the input to the cell to a low logic state, and writing a second logic state on the write data line drives the input to the cell to a high logic state. The multi-port register has application for use in a superscalar microprocessor performing out-of-order dispatch and execution and speculative execution.

Multi-port register

A multi-port register contains a plurality of cells each capable of storing at least two states. The cells contain at least one read and one write port. Each read port contains a corresponding read enable line, a read data line, and a read transistor stack. Each write port contains a corresponding write enable line, write data line, and a write transistor stack. The read data line is coupled to a pre-charge circuit that charges the read data line to a predetermined threshold level prior to reading the contents of the cell. The read transistor stack couples the output of the cell to the corresponding read data line such that the read data line is pulled to ground when the cell stores a first logic state, and the read data line retains the pre-determined voltage state when the cell stores the second logic state. The write transistor stack couples the write data line to the cell such that writing a first logic state on the write data line pulls the input to the cell to a low logic state, and writing a second logic state on the write data line drives the input to the cell to a high logic state. The multi-port register has application for use in a superscalar microprocessor performing out-of-order dispatch and execution and speculative execution.

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Aloha, OR, United States of America

Wesley D McCullough