Infineon Technologies Ag

Siemens Aktiengesellschaft

Infineon Technology Ag

Werner Schwetlick

Matthias Stecher

Tim Gutheit

Thorsten Meyer

Andreas Peter Meiser

Harald Gossner

Robert Zink

Karsten Mosig

A semiconductor device includes a semiconductor body having a first surface and a second surface opposite to the first surface, first trenches and second trenches extending from the first surface into the semiconductor body, at least one lateral IGFET including a first load terminal at the first surface, a second load terminal at the first surface and a gate electrode within the first trenches, and at least one vertical IGFET including a first load terminal at the first surface, a second load terminal at the second surface and a gate electrode within the second trenches. The first trenches extend from the first surface into the semiconductor body deeper than a channel zone of the lateral IGFET and confine the channel zone.

Semiconductor device including at least one lateral IGFET and at least one vertical IGFET and corresponding manufacturing method

A semiconductor device includes a stripe-shaped electrode structure that extends from a first surface into a semiconductor portion. The electrode structure includes a main portion and an end portion terminating the electrode structure. The main portion includes a field electrode and a first portion of a field dielectric separating the field electrode from the semiconductor portion. The end portion includes a filled section in which a second portion of the field dielectric extends from a first side of the electrode structure to an opposite second side. The filled section is narrower than the main portion and a length of the filled section along a longitudinal axis of the electrode structure is at least 150% of a first layer thickness of the first portion of the field dielectric.

Stripe-shaped electrode structure including a main portion with a field electrode and an end portion terminating the electrode structure

A semiconductor device includes a semiconductor body having a first surface and a second surface opposite to the first surface. The semiconductor device further includes first and second trenches extending from the first surface into the semiconductor body. The semiconductor device further includes at least one lateral IGFET including a first load terminal at the first surface, a second load terminal at the first surface and a gate electrode within the first trenches. The semiconductor device further includes at least one vertical IGFET including a first load terminal at the first surface, a second load terminal at the second surface and a gate electrode within the second trenches.

Semiconductor device and method of manufacturing the same

A semiconductor device is formed in a semiconductor substrate comprising a first main surface and includes a control gate disposed in a lower portion of a first trench formed in the first main surface, a floating gate disposed in the first trench above the control gate and insulated from the control gate, a source region of a first conductivity type, a body region of a second conductivity type, and a drain region of the first conductivity type.

Semiconductor device, integrated circuit and method of manufacturing an integrated circuit

A method for fabricating an integrated electronic circuit includes producing electrically active elements in the region of one plane. At least one insulation layer and at least one contact-making layer are applied on the electrically active elements, and subsequently at least one connecting wire is applied to the contact-making layer. The contact-making layer is produced in such a way that the contact-making layer has a thickness which is at least 10% of the radius of the connecting wire. An integrated electronic circuit is fabricated with the aid of the method.

Method for fabricating an integrated electronic circuit and integrated electronic circuit

Additional degrees of freedom are provided for optimizing the component properties by combining two doping profiles. The threshold voltage of NMOS or DMOS transistors can be set through the process parameters involved in the introduction and outward diffusion of the further dopant of the second conductivity type, independently of the deep concentration, since the dopant concentration at the surface can be chosen independently of the dopant concentration at depth. A low film resistance results from the great penetration depth of the semiconductor region through the combination of the two dopant profiles. The low film resistance leads to reduced pinching of the substrate current in an NMOS transistor, and to greater stability against &ldquo;latch-up&rdquo;, without substantially increasing the concentration of the dopants in the region of source/drain diffusions, and therefore without unfavorably affecting drain/bulk capacitance. In addition, the concentration of the further dopant of the second conductivity type can be kept low. A semiconductor region of a second conductivity type is thus attained which exhibits little outward lateral diffusion. Further, when the components are given the conventional polarity, the semiconductor region is insulated from the p-substrate by the buried zone.

Method of producing a transistor structure

An integrated semiconductor circuit has a protection structure for protecting against electrostatic discharge. The protection element has at least one integrated vertical protection transistor, whose load path is connected between the terminal pad and a potential rail. The base of the vertical npn bipolar transistor is controlled by a diode at breakdown, whose breakdown voltage is above the holding voltage of the npn bipolar transistors. By suitably choosing the location of the base contact, of the pn junction of the breakdown diode, and of the emitter, a desired adjustment of the trigger current is possible. Thus a variation in the voltage drop at the base is achieved which enables a current flow. The signal voltage requirements can be met and at the same time, an optimization of the ESD strength is achieved. The control or trigger sensitivity of the base can also be adjusted by means of an integrated resistor, which is disposed in the base zone.

Integrated semiconductor circuit with protection structure for protecting against electrostatic discharge

Bridged, doped zones are formed in a semiconductor. A silicon nitride layer is deposited and structured on a semi-conductor region with a predetermined dopant concentration. The structure is subjected to thermal oxidation, with the result that at least one oxide region and at least two oxide-free regions, which are separated from one another by the oxide region, are produced on the surface of the semiconductor region. A dopant is introduced into the oxide-free regions and driven into the semiconductor region. A coherent zone is thus produced in the semiconductor region with a dopant concentration at least ten times the dopant concentration of the semiconductor region. This produces a coherent zone having a high dopant concentration which is bridged by the oxide region which separates the oxide-free regions on the surface of the semiconductor region. Conductive layers, such as a polysilicon layer or a metal layer, for example, can be formed on the oxide region (oxide bridge), with the assurance the conductive layer is completely insulated from the doped zone.

Growing community of inventors

Groebenzell, Germany

Werner Schwetlick