Infineon Technologies Ag

Infineon Technologies Austria Ag

Werner Schustereder

Hans-Joachim Schulze

Johannes Georg Laven

Moriz Jelinek

Anton Mauder

Hans Weber

Alexander Breymesser

Roland Rupp

Franz Hirler

Holger Schulze

Helmut Oefner

Wolfgang Jantscher

Caspar Leendertz

Daniel Tutuc

Andreas Voerckel

Maximilian Treiber

Ralf Siemieniec

Romain Esteve

Wolfgang Lehnert

Ravi Keshav Joshi

Ingo Muri

Stephan Voss

Friedrich Kroener

Franz Josef Niedernostheide

Roman Knoefler

Markus Bina

Michael Stadtmueller

Tobias Franz Wolfgang Hoechbauer

Alexander Susiti

Mihai Draghici

Axel Koenig

Michael Brugger

Dieter Fuchs

Naveen Goud Ganagona

Markus Zundel

Edward Fuergut

Francisco Javier Santos Rodriguez

Oliver Blank

Helmut Strack

Roman Baburske

Gerhard Schmidt

Jens Peter Konrath

Bernhard Goller

Irmgard Escher-Poeppel

Maximilian Roesch

Carsten Schaeffer

Juergen Steinbrenner

Rudolf Berger

Marko Swoboda

Andreas Riegler

Paul Ganitzer

Thomas Christian Neidhart

Thomas Gutt

Christian Krueger

Guenter Denifl

Oliver Humbel

Christian Kampen

Gerhard Poeppel

Manfred Pippan

Josef Georg Bauer

Paul Ellinghaus

Mario Barusic

Petra Fischer

Alexander Binter

Karl-Heinz Bach

Peter Zupan

Jyotshna Bhandari

Waqas Mumtaz Syed

Kurt Pekoll

Sandeep Walia

Kristijan Luka Mletschnig

Stanislav Vitanov

Thomas Neidhart

Hans Millonig

Harald Wiedenhofer

Guenther Wellenzohn

Stephanie Fassl

Michael Kokot

Axel König

Gerald Patterer

Bernhard Leitl

A method of manufacturing a metal silicide layer comprises performing laser thermal annealing of a surface region of a silicon carbide (SiC) substrate, exposing a surface of a thus obtained silicon layer, depositing a metal layer above the exposed silicon layer, and/or thermally treating a stack of layers, comprising the silicon layer and the metal layer, to form a metal silicide layer. Alternatively and/or additionally, the method may comprise depositing a silicon layer above a SiC substrate, depositing a metal layer, and/or performing laser thermal annealing of the SiC substrate and a stack of layers above the SiC substrate to form a metal silicide layer, wherein the stack of layers comprises the silicon layer and the metal layer. Moreover, a semiconductor device is described, comprising a SiC substrate, a metal silicide layer, and a polycrystalline layer in direct contact with the SiC substrate and the metal silicide layer.

Method of manufacturing a metal silicide layer above a silicon carbide substrate, and semiconductor device comprising a metal silicide layer

The present disclosure relates to methods of manufacturing Ohmic contacts on a silicon carbide (SiC) substrate including providing a 4H—SiC or 6H—SiC substrate, implanting dopants into a surface region of the 4H—SiC or 6H—SiC substrate, annealing the implanted surface regions to form a 3C—SiC layer, and depositing a metal layer on the 3C—SiC layer. An implanting sequence of the implantation of dopants includes a plurality of plasma deposition acts with implantation energy levels including at least two different implantation energy levels. The implantation energy levels and one or more implantation doses of the plurality of plasma deposition acts are selected to form a 3C—SiC layer in the surface region of the 4H—SiC or 6H—SiC substrate during the annealing act. A method of manufacturing a semiconductor device having a structure including at least three layers including a 4H—SiC or 6H—SiC layer, a 3C—SiC layer, and a metal layer, by applying one or more of the techniques described herein, and semiconductor devices obtained with one or more of the techniques described herein are described.

Method of manufacturing ohmic contacts on a silicon carbide (SIC) substrate, method of manufacturing a semiconductor device, and semiconductor device

The application relates to a semiconductor power device including a semiconductor body in which a transistor device is formed, the transistor device having a gate region and a channel region laterally aside the gate region, the gate region including a gate electrode for controlling a channel formation in the channel region, and a gate dielectric laterally between the channel region and the gate electrode. The gate electrode includes a gate electrode bulk region and a gate electrode layer laterally between the gate dielectric and the gate electrode bulk region. The gate electrode layer is made of a doped metallically conductive material.

Semiconductor power device and method of manufacturing the same

A method includes orienting a silicon carbide layer to a first crystal channel direction relative to a first ion beam and implanting phosphorous into the silicon carbide layer using the first ion beam to define a first doped region in the silicon carbide layer. A deviation angle between the first crystal channel direction and the first ion beam is less than ±1° and the first crystal channel direction comprises a <0001> direction or a <11-23> direction.

Semiconductor device fabricated using channeling implant

A method for fabricating a semiconductor device includes: forming a trench in a first major surface of a semiconductor body having a first conductivity type; forming a gate in the trench; forming a body region of a second conductivity type in the semiconductor body; implanting a second dopant species into a first region of the body region and a first dopant species into a second region of the body region, the first dopant species providing the first conductivity type, the second dopant species being different from the first dopant species and reducing the diffusion of the first dopant species in the semiconductor body; and thermally annealing the semiconductor body to form a source region that includes the first and second dopant species, and to produce a pn-junction between the source and body regions at a depth dfrom the first major surface, wherein 50 nm&#x3c;d&#x3c;300 nm.

Method for manufacturing a semiconductor device

A silicon carbide substrate is provided that includes a drift layer of a first conductivity type and a trench extending from a main surface of the silicon carbide substrate into the drift layer. First dopants are implanted through a first trench sidewall of the trench. The first dopants have a second conductivity type and are implanted at a first implant angle into the silicon carbide substrate, wherein at the first implant angle channeling occurs in the silicon carbide substrate. The first dopants form a first compensation layer extending parallel to the first trench sidewall.

Silicon carbide device with compensation region and method of manufacturing

Methods for processing a semiconductor substrate are proposed. An example of a method includes forming cavities in the semiconductor substrate by implanting ions through a first surface of the semiconductor substrate. The cavities define a separation layer in the semiconductor substrate. A semiconductor layer is formed on the first surface of the semiconductor substrate. Semiconductor device elements are formed in the semiconductor layer. The semiconductor substrate is separated along the separation layer into a first substrate part including the semiconductor layer and a second substrate part.

Methods for processing a semiconductor substrate

First dopants are implanted through a larger opening of a first process mask into a silicon carbide body, wherein the larger opening exposes a first surface section of the silicon carbide body. A trench is formed in the silicon carbide body in a second surface section exposed by a smaller opening in a second process mask. The second surface section is a sub-section of the first surface section. The larger opening and the smaller opening are formed self-aligned to each other. At least part of the implanted first dopants form at least one compensation layer portion extending parallel to a trench sidewall.

Silicon carbide device with compensation layer and method of manufacturing

Forming a semiconductor arrangement includes providing a first semiconductor layer having a first surface, forming a first plurality of trenches in the first surface of the first semiconductor layer, each of the trenches in the first plurality having first and second sidewalls that extend from the first surface to a bottom of the respective trench, implanting first type dopant atoms into the first and second sidewalls of each of the trenches in the first plurality, implanting second type dopant atoms into the first and second sidewalls of each of the trenches in the first plurality, and annealing the semiconductor arrangement to simultaneously activate the first type dopant atoms and the second type dopant atoms.

Method for producing a superjunction device

An apparatus for processing a plurality of semiconductor wafers, the apparatus including a spallation chamber, a neutron producing material mounted in the spallation chamber, a neutron moderator, and an irradiation chamber coupled to the spallation chamber, wherein the neutron moderator is disposed between the spallation chamber and the irradiation chamber, wherein the irradiation chamber is configured to accommodate the plurality of semiconductor wafers, wherein each of the plurality of semiconductor wafers has a first surface and a second surface opposite the first surface, wherein the plurality of semiconductor wafers are positioned so that a first surface of one semiconductor wafer faces a second surface of another semiconductor wafer.

Apparatus and method for neutron transmutation doping of semiconductor wafers

An ion implantation method includes changing an ion acceleration energy and/or an ion beam current density of an ion beam while effecting a relative movement between a semiconductor substrate and the ion beam impinging on a surface of the semiconductor substrate.

Ion implantation method, ion implantation apparatus and semiconductor device

In an embodiment, a semiconductor device is provided. The semiconductor device includes: a semiconductor body of a first conductivity type having opposing first and second major surfaces; a gate arranged in a trench extending into the semiconductor body from the first major surface; a body region of a second conductivity type; a source region of the first conductivity type arranged on the body region and having first and second dopant species. The source region forms a pn-junction with the body junction, the pn-junction being arranged at a depth dfrom the first major surface, wherein 50 nm&#x3c;d&#x3c;300 nm. A drain region of the first conductivity type is arranged in the semiconductor body under the trench.

Semiconductor device and method for manufacturing a semiconductor device

A method of manufacturing a semiconductor device includes reducing a thickness of a semiconductor substrate and/or forming a doped region in the semiconductor substrate. The method further includes changing an ion acceleration energy of an ion beam while effecting a relative movement between the semiconductor substrate and the ion beam impinging on the semiconductor substrate.

Method of manufacturing a semiconductor device by using ion beam technique

Crystal lattice vacancies are generated in a pretreated section of a semiconductor layer directly adjoining a process surface. Dopants are implanted at least into the pretreated section. A melt section of the semiconductor layer is heated by irradiating the process surface with a laser beam activating the implanted dopants at least in the melt section.

Semiconductor devices with steep junctions and methods of manufacturing thereof

A method for processing a silicon carbide wafer includes implanting ions into the silicon carbide wafer to form an absorption layer in the silicon carbide wafer. The absorption coefficient of the absorption layer is at least 100 times the absorption coefficient of silicon carbide material of the silicon carbide wafer outside the absorption layer, for light of a target wavelength. The silicon carbide wafer is split along the absorption layer at least by irradiating the silicon carbide wafer with light of the target wavelength to obtain a silicon carbide device wafer and a remaining silicon carbide wafer.

Methods for processing a silicon carbide wafer, and a silicon carbide semiconductor device

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Villach, Austria

Werner Schustereder