Licentia Patent-verwaltungs Gmbh

Deutsche Thomson-brandt Gmbh

Telefunken Fernseh Und Rundfunk Gmbh

Ted Bildplatten Aktiengesellschaft, Aeg-telefunken, Teldec

Ted Bildplatten Aktiengesellschaft

Werner Scholz

Hartmut Peters

Friedrich Timmermann

Bernd Wessolly

Peter Mahr

Paul-Louis Meunier

Klaus Oldermann

Walter Voessing

Gerhard Reiner

Max Artigalas

Wulf-Christian Streckenbach

Juergen Kaaden

Martin Kuner

Ernst F Schroeder

Gerald Dickopp

Gerhard Mahler

Werner Bachnick

Andreas Kluger

A magnetic tape apparatus for the recording and reproduction of signals, including a magnetic tape having plural data tracks running parallel to an edge of the tape; a multi-track reading device including a multi-track playback head configured to read simultaneously plural of the tracks and output signals corresponding to data recorded on the plural tracks; and a housing in which the tape and the reading device are permanently disposed; wherein the tape is adapted for simultaneous recording of data onto plural data tracks of the tape via external recording heads upon the apparatus being connected to an external recording facility.

Magnetic tape apparatus with housing in which playback electronics and

The invention relates to a method for recording longitudinal track bundles on an information medium. The method involves recording tracking information in special tracks in said track bundles. The special tracks are contiguous between each other. When recording a new track bundle a recording and/or reading head may be positioned using tracking information contained in special tracks of a previously recorded track bundle. Several examples of patterns used for coding tracking information in the special tracks we described.

Recording method and information medium for a plurality of longitudinal

Low-redundancy codes are increasingly being striven for, such codes thus inevitably requiring comparatively long code words. However, since the memory requirement for coding tables increases considerably with the length of the code words, the use of code tables is then no longer expedient. Instead, coding is then effected by selecting the optimum code word in each case from a plurality of different code words taking account of coding; prescriptions and spectral decisions. For this purpose, the maximum run length for each code word is also determined, inter alia, but the spectral decisions are decisive as long as the maximum run length does not exceed a predetermined maximum value. Provided that the end of one code word and the beginning of a succeeding code word have the same binary value, incorrect decisions in the selection of the optimum code word may arise in the region where the synchronizing pattern is keyed in. According to the invention, therefore, the bit pattern (16) serving for synchronization is changed (17) prior to the determination of the code word which is optimum for generating the signal.

Method and circuit arrangement for the generation of a channel-coded

A signal regenerator for binary signals includes a signal equalizer having an input filter and an integrator. An amplitude detector and a period detector are arranged to receive the output signal of the equalizer. A high pass filter is included in a feedback loop to feed the output signal of one of the detectors back to the equalizer.

Signal regenerator for binary signals

A decoding circuit for 2T encoded binary signals, comprises: a data input terminal; a first D-type flip flop having an input coupled to the input terminal; a first exclusive OR gate having inputs coupled to the input terminal and an output of the first D-type flip flop; a shift register having an input coupled to an output of the exclusive OR gate; a second D-type flip flop having an input coupled to the shift register; and, a second exclusive OR gate having inputs coupled to an output of the second D-type flip flop and to a tap of the shift register, the second exclusive OR gate having an output at which decoded input signals are reconstituted. The second D-type flip flop may be a constituent stage of the shift register, the inputs of the second exclusive OR gate being coupled to adjacent taps of the shift register. At least one of the adjacent taps is the output of the constituent stage formed by the second D-type flip flop. A gate arrangement is coupled to a plurality of taps of the shift register for decoding a predetermined bit pattern in the input signal, for example, a synchronizing component of a digitally recorded video signal played back to the data input terminal. The consecutive taps of the shift register are chosen for equalizing a delay time between detection of the synchronizing component and the reconstituted video signal.

Circuit for decoding 2T encoded binary signals

An apparatus for distinguishing a wanted signal in a binary signal sequence having both wanted signals and interference signals includes the step of generating a correction value which has a first value to indicate a wanted binary signal and a second value to indicate a binary interference signal. The wanted signal has a preselected maximum number of bits. A first counter counts the bits of the binary signal sequence and changes the correction value from the first value to the second value when the preselected maximum is exceeded. The correction value is reset to the first value when the temporal spacing between two occurrences of excesses of the preselected maximum number exceeds a predetermined spacing.

Method and apparatus for recognizing valid components in a digital signal

A circuit for developing a binary bitstream signal from a ternary analog signal having positive and negative amplitude peaks includes an analog-to-digital converter for receiving the analog signal and providing digital samples in accordance with the amplitude and polarity of the analog signal. The most significant bit of digital sample indicates the polarity of an analog signal sample. A threshold value is compared to a current amplitude sample to indicate a level change in the analog signal when the sample value exceeds the threshold value and the polarity differs from that of the preceding sample which exceeded the threshold value. The current sample value which exceeds the threshold value is compared with preceding sample values which exceeded the threshold value, and a level change is indicated by the sample value which most exceeds the threshold value. Incorrect sample values are inverted in a correction circuit.

Method and circuit for regenerating a binary bit stream from a ternary

For the transmission of synchronizing information for a PCM signal transmitted in biphase code, a synchronizing pattern is provided which is composed of a biphase signal that has been shifted by one-half bit period relative to the data portion of the transmitted signal.

Synchronizing pattern

Phase control circuit

When recording a PCM signal, particularly an audio signal, on the oblique tracks of a magnetic tape, e.g. for example of a videorecorder, errors occur in the digital signal during the change of heads. These errors are removed in that, in the region where the scanning of the heads overlaps, phase matching of the bit clock pulses is effected, the bit patterns are matched and the number of bit clock pulses is increased or reduced before the next change of heads.

Playback device for a digital signal recorded by a plurality of heads

In a circuit arrangement for the correction of falsified sample values in a PCM transmission system, which arrangement includes an interpolation member connected for deriving a corrected value to replace each falsified value by interpolation between sample values preceding and succeeding the falsified value in time, the interpolation member is provided with components connected for deriving each corrected value by effecting a weighted combination of the sample value appearing at the output of the interpolation member and preceding the falsified value in time and the next unfalsified sample value succeeding the falsified value in time in order to perform an at least approximately linear interpolation between sample values which are thus combined.

Circuit for correcting distortions in a PCM transmission device

In a system for processing PCM signals and transmitting such signals over a channel, which system includes an input portion having a circuit for interleaving arriving data words and supplying the interleaved words to the input end of the channel, and an output portion having a circuit for de-interleaving the data words arriving at the output end of the channel so that the data words, after de-interleaving, are present in the sequence existing before interleaving, the interleaving circuit performs two successive interleaving operations on the arriving data words, and the de-interleaving circuit operates in a manner to complement the interleaving circuit.

PCM Signal system

In a circuit for processing a useful signal which varies in amplitude between positive and negative values about a zero value and contains information in the locations of its zero passages, which circuit includes: a zero passage detector having an input; a first capacitor connected in series between a source of the useful signal and the detector input; and components for coupling the useful signal with a first equalizing signal during the positive value intervals of the useful signal and with a second equalizing signal during the negative intervals of the useful signal, the coupling components include sources of the two equalizing signals, controllable switches connected to each source for selectively coupling the corresponding equalizing signal with the useful signal; and a control pulse generator means connected for applying to each said switch control pulses derived from the useful signal and having a timing such that each switch is closed for a predetermined period during its associated intervals of the useful signal.

Circuit for processing a digital signal

In a modulation and demodulation system for converting a binary sequence composed of a succession of bits, each having a value of '1' or '0', occurring in successive bit intervals, into a transmitted signal containing a representation of each bit, by representing a bit of one value as a change in the level of the transmitted signal at a time corresponding to the middle of the associated bit interval, and representing a bit of the other value as a change in the level of the transmitted signal at a time corresponding to the end of the associated bit interval if a further bit of the other value follows, transmitted signal level changes associated with the bits of the other value are in part suppressed for causing the time period between level changes in the transmitted signal to be no longer than the period of more than two consecutive level changes at intervals equal to each bit interval and associated with the bits of the other value.

Modulator and demodulator circuits for modified delay modulation method

A non-inverting amplifier circuit having input and output terminals wherein the input impedance between the input terminal and a reference point is relatively low. The circuit comprises a first amplifier having a non-inverting input coupled to the input terminal, an inverting input, and an output coupled to the output terminal. A second amplifier is also provided, the second amplifier having a non-inverting input, an inverting input coupled to the output of the first amplifier and an output coupled to the non-inverting input of the first amplifier.

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Gehrden, Germany

Werner Scholz