Infineon Technologies Ag

Siemens Aktiengesellschaft

Nissan Chemical Corporation

Werner Pamler

Zvonimir Gabric

Siegfried Schwarzl

Guenther Schindler

Manfred Engelhardt

Volker Weinrich

Hermann Wendt

Gunther Schindler

Eugen Unger

Günther Schindler

Franz Richter

Andreas Stich

Gernot Steinlesberger

Martin Traving

Andreas Gross

Madeleine Piekass

Andreas Luible

An interconnect arrangement and fabrication method are described. The interconnect arrangement includes an electrically conductive mount substrate, a dielectric layer formed on the mount substrate, and an electrically conductive interconnect formed on the dielectric layer. At least a portion of the dielectric layer under the interconnect contains a cavity. To fabricate the interconnect arrangement, a sacrificial layer is formed on the mount substrate and the interconnect layer is formed on the sacrificial layer. The interconnect layer and the sacrificial layer are structured to produce a structured interconnect on the structured sacrificial layer. A porous dielectric layer is formed on a surface of the mount substrate and of the structured interconnect as well as the sacrificial layer. The sacrificial layer is then removed to form the cavity under the interconnect.

Interconnect arrangement and associated production methods

In a method for manufacturing a layer arrangement, a plurality of electrically conductive structures are embedded in a substrate. Material of the substrate is removed at least between adjacent electrically conductive structures. An interlayer is formed on at least one portion of sidewalls of each of the electrically conductive structures. A first layer is formed on the interlayer where an upper partial region of the interlayer remaining free of a covering with the first layer. An electrically insulating second layer is formed selectively on that partial region of the interlayer which is free of the first layer, in such a way that the electrically insulating second layer bridges adjacent electrically conductive structures such that air gaps are formed between adjacent electrically conductive structures.

Method for manufacturing a layer arrangement and layer arrangement

A method for producing a layer arrangement is disclosed. A layer of oxygen material and nitrogen material is formed over a substrate that has a plurality of electrically conductive structures and/or over a part of a surface of the electrically conductive structures. The layer is formed using a plasma-enhanced chemical vapor deposition process with nitrogen material being supplied during the supply of silicon material and oxygen material by means of an organic silicon precursor material. The layer of oxygen material and nitrogen material is formed in such a manner that an area free of material remains between the electrically conductive structures. An intermediate layer including an electrically insulating material is formed over the layer of oxygen material and nitrogen material. A covering layer is selectively formed over the intermediate layer such that the area free of material between the electrically conductive structures is sealed from the environment and forms a cavity.

Plasma excited chemical vapor deposition method silicon/oxygen/nitrogen-containing-material and layered assembly

A process for producing a layer arrangement, in which a plurality of electrically conductive structures are formed on a substrate, a first electrically insulating layer is formed on the plurality of electrically conductive structures, in such a manner than trenches are formed between mutually adjacent regions of the first electrically insulating layer, electrically insulating structures are formed in the trenches between the adjacent regions of the first electrically insulating layer, material of the first electrically insulating layer is removed, so that airgaps are formed between the electrically insulating structures and the electrically conductive structures, and a second electrically insulating layer is formed on the electrically conductive structures and on the electrically insulating structures, in such a manner that the second electrically insulating layer spans adjacent electrically conductive structures and electrically insulating structures.

Layer arrangement

A pattern of voids in an integrated circuit having a first layer, a first layer surface and adjacent lands on the first layer surface, the adjacent lands enclosing spaces and including a second layer of a first isolation material and a third layer of a second isolation material arranged on the second layer. The pattern of voids has a fourth layer of a third isolation material which closes off at least some of the spaces and cannot be deposited on the first isolation material. The fourth layer is arranged on the third layer and has a second layer surface. Spaces that are not closed off by means of the fourth layer are filled with electrically conductive material. In the method for producing a pattern of voids in an integrated circuit, a second layer of a first isolation material is applied to a first layer surface of a first layer. A third layer of a second isolation material is applied to the second layer, the third layer acquiring a second layer surface which is arranged parallel to the first layer surface. Adjacent lands with spaces are formed from the second layer and the third layer. A third isolation material is selectively applied on the adjacent lands to the third layer, such that a fourth layer is formed between and above the adjacent lands. Parallel to the first layer surface, the fourth layer is partially removed until the second layer surface is uncovered. The fourth layer is completely removed above some spaces, and finally these spaces are filled with electrically conductive material in order to form electrical contacts between the first layer surface and the second layer surface, resulting in a pattern of voids.

Hollow structure in an integrated circuit and method for producing such a hollow structure in an integrated circuit

The electrode configuration includes at least one structured layer. A mask is produced on the layer to be structured and the layer is dry etched. The mask is at least slightly etchable by dry etching. The mask contains a metal silicide, a metal nitride or a metal oxide.

Method of producing an electrode configuration and method of electrically contacting the electrode configuration

An interconnect arrangement comprises a substrate made from a first insulating material with a substrate surface, at least two interconnects which are arranged next to one another in the substrate, a buffer layer made from a second insulating material above the substrate and comprising a buffer-layer surface, which is parallel to the substrate surface, at least one cavity, which is arranged between the interconnects and, with respect to the buffer-layer surface, extends deeper into the substrate than the interconnects, and a covering layer made from a third insulating material, which is arranged above the buffer layer and completely closes off the cavity with respect to the buffer-layer surface.

Strip conductor arrangement and method for producing a strip conductor arrangement

A method referred to as a 'cellular damascene method' utilizes a multiplicity of regularly arranged closed cavities referred to as 'cells', which are produced in a patterning layer. The dimensions of the cavities are on the order of magnitude of the microstructures to be produced. Selected cavities are opened by providing a mask and partitions situated between adjacent opened cavities are removed to provide trenches and holes which are filled with the material of the microstructure to be fabricated. Protruding material is removed by means of a chemical-mechanical polishing step. The microstructures are, in particular, interconnects and contact holes of integrated circuit.

Arrangement of microstructures

A method referred to as a &ldquo;cellular damascene method&rdquo; utilizes a multiplicity of regularly arranged closed cavities referred to as &ldquo;cells&rdquo;, which are produced in a patterning layer. The dimensions of the cavities are on the order of magnitude of the microstructures to be produced. Selected cavities are opened by providing a mask and partitions situated between adjacent opened cavities are removed to provide trenches and holes which are filled with the material of the microstructure to be fabricated. Protruding material is removed by means of a chemical-mechanical polishing step. The microstructures are, in particular, interconnects and contact holes of integrated circuit.

Method for fabricating microstructures and arrangement of microstructures

A method for improving the adhesion between a noble metal layer and an insulation layer includes configuring a silicon layer between the noble metal layer and the insulation layer. The silicon layer is siliconized and oxidized by a thermal treatment in an oxidative environment, resulting in an oxidized silicide layer with high intermixing of the noble metal and the formed oxide. The relatively large inner surface achieved as a result improves the adhesion between the noble metal layer and the insulation layer.

Method for fabricating a component, and component having a metal layer and an insulation layer

Metal structures that can be produced by a damascene process are disposed in a first insulating layer and a second insulating layer is disposed above the latter. There is in each case at least one cavity which is disposed between the metal structures, is disposed in the first insulating layer and is covered by the second insulating layer. The cavities and the metal structures are produced next to one another by self-aligned process steps.

Substrate with at least two metal structures deposited thereon, and method for fabricating the same

For fastening a first substrate (11) on a second substrate (21), gallium is selectively deposited on the surface of electrically conductive structures (18) located on the first substrate (11), being deposited in a CVD process upon employment of a metalloorganic compound. After the joining of the substrates (11, 21), the gallium (19) is mixed with a metal (28) that forms a refractory intermetallic phase with gallium, this forming a firm connection between the substrates. The method can be especially utilized for cubic integration.

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Munich, Germany

Werner Pamler