Siemens Aktiengesellschaft

Werner M Klingenstein

Wolfgang H Krautschneider

Doris Schmitt-Landsiedel

Heinz Zeininger

In the manufacture of semiconductor devices on a single substrate, said devices comprising a source region, a drain region and a gate therebetween, forming an isolation region after formation of the gate between said devices, thereby reducing required tolerances between devices and rows of devices and minimizing space requirements on the substrate for the array. A conventional isolation region between adjacent devices can be formed first, the layers comprising the gate deposited, the gate formed by etching through the layers, and a second isolation region between rows of devices formed after the gate etch. This reduces the built-in tolerances required between rows of devices, and reduces the spacing requirements between the rows.

Transistor isolation process

An integrated polysilicon diode contact having multiple doped layers. A first highly doped layer of a first dopant type is deposited on a silicon substrate. A second highly doped layer of a second, different dopant type is deposited on the substrate, separated by a spacer from the first highly doped layer. A third lower doped layer of the second dopant type is deposited on the first highly doped layer and second highly doped layers, the third lower doped layer forming a p-n junction with a source region having a dopant of the first type.

Integrated polysilicon diode contact for gain memory cells

In a method of determining the possible formation of crystalline defects in a body of a semiconductor material during the process of fabricating integrated circuits in the body, at least one body is subjected to a full fabrication process to form completed integrated circuits in the body which can be electrically tested to determine whether the operation of the integrated circuit is adversely affected by the formation of crystalline defects. Test structures, each of which is only a portion of the complete integrated circuit, are formed during the formation of the complete circuit but are fabricated using only a group of a limited number of the steps of the fabrication process used to fabricate the complete integrated circuit with various ones of the test structures being subjected to different ones of the steps of the group of steps. The test structures may be formed on the same body as the complete circuit or on additional bodies. The test structures are then analyzed to determine which of the steps may have formed crystalline defects in the body.

Method of defect determination and defect engineering on product wafer

A multistep process is disclosed that provides an economical process for making a gain memory cell array using self-aligned techniques; that provides an integrated diode in the gate stack of the storage transistor; that provides a buried V.sub.DD line to connect the drains of the storage transistors to the power supply; and that provides a buried strap to connect the integrated diode to the source region of the storage transistor.

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Kirchheim, Germany

Werner M Klingenstein