Lumileds Lighting U.s., LLC

Philips Lumileds Lighting Company LLC

Lumileds LLC

Koninklijke Philips Corporation N.V.

Xerox Corporation

Lumileds Holding B.v.

Werner K Goetz

Nathan Fredrick Gardner

Michael David Camras

R Scott Kern

John Edward Epler

Michael Jason Grundmann

Melvin Barker Mclaurin

Stephen Andrew Stockman

Chihping Kuo

David P Bour

Linda T Romano

Changhua Chen

Aurelien Jean Francois David

Paul Scott Martin

Daniel Alexander Steigerwald

Patrick Nolan Grillot

Christopher P Kocot

Anneli Munkholm

Gina L Christenson

Andrew Y Kim

Michael Ragan Krames

Noble Marshall Johnson

Tetsuya Takeuchi

Ghulam Hasnain

Wouter Anthon Soer

Mark R Hueschen

Qi Ye

Junko Kobayashi

Nathan Frederick Gardner

Thomas L Paoli

Gerd O Mueller

Yu-Chen Shen

Richard P Schneider

Ross D Bringans

Jack A Walker

G A Connell

Satoshi Watanabe

Reena Khare

Fernando A Ponce

Richard Scott Kern

Xiaoping Chen, Legal Representative

Gangyi Chen

Francisco Alexander Leon

Melvin Barker McLaurin

Nathan E Gardner

Tunable LED lighting systems, devices and methods are described herein. A light emitting device includes at least a first phosphor-converted LED configured to emit light having a desaturated orange color point characterized by CIE 1976 color coordinates 0.3&#x3c;u'&#x3c;0.35 and v&#x2032;&#x3e;0.52 and at least a second phosphor-converted LED configured to emit light having a cyan color point characterized by CIE 1976 color coordinates 0.15&#x3c;u&#x2032;&#x3c;0.20 and 0.47&#x3c;v&#x2032;&#x3c;0.52. The first phosphor-converted LED and the second phosphor-converted LED are arranged to combine the light emitted by the first phosphor-converted LED with the light emitted by the second phosphor-converted LED to provide a white light output from the light emitting device.

Color tunable light emitting diode (LED) systems, LED lighting systems, and methods

Methods and apparatus are described. An apparatus includes a hexagonal oxide substrate and a III-nitride semiconductor structure adjacent the hexagonal oxide substrate. The III-nitride semiconductor structure includes a light emitting layer between an n-type region and a p-type region. The hexagonal oxide substrate has an in-plane coefficient of thermal expansion (CTE) within 30% of a CTE of the III-nitride semiconductor structure.

Light emitting device with improved extraction efficiency

A device includes a substrate () and a III-nitride structure () grown on the substrate, the III-nitride structure comprising a light emitting layer () disposed between an n-type region () and a p-type region (). The substrate is a RA0(MO)where R is one of a trivalent cation: Sc, In, Y and a lanthanide; A is one of a trivalent cation: Fe (III), Ga and Al; M is one for a divalent cation: Mg, Mn, Fe (II), Co, Cu, Zn and Cd; and n is an integer&#x2265;1. The substrate has an inplane lattice constant a. At lease one III-nitride layer in the III-nitride structure has a bulk lattice constant asuch that [(|a&#x2212;a|)/a]*100% is no more than 1%.

III-nitride light emitting device with a region including only ternary, quaternary, and/or quinary III-nitride layers

In a method according to embodiments of the invention, a III-nitride layer is grown on a growth substrate. The III-nitride layer is connected to a host substrate. The growth substrate is removed. The growth substrate is a non-III-nitride material. The growth substrate has an in-plane lattice constant a. The III-nitride layer has a bulk lattice constant a. In some embodiments, [(|a&#x2212;a|)/a]*100% is no more than 1%.

Method of forming a composite substrate

In embodiments of the invention, a semiconductor structure comprising a III-nitride light emitting layer disposed between an n-type region and a p-type region is grown on a substrate. The substrate is a non-III-nitride material. The substrate has an in-plane lattice constant a. At least one III-nitride layer in the semiconductor structure has a bulk lattice constant aand [(|a&#x2212;a|)/a]*100% is no more than 1%. A surface of the substrate opposite the surface on which the semiconductor structure is grown is textured.

In a method according to embodiments of the invention, a III-nitride layer is grown on a growth substrate. The III-nitride layer is connected to a host substrate. The growth substrate is removed. The growth substrate is a non-III-nitride material. The growth substrate has an in-plane lattice constant a substrate. The III-nitride layer has a bulk lattice constant a layer. In some embodiments, [(|substrate&#x2212;a layer|)/substrate]*100% is no more than 1%.

In embodiments of the invention, a semiconductor structure comprising a III-nitride light emitting layer disposed between an n-type region and a p-type region is grown on a substrate. The substrate is a non-III-nitride material. The substrate has an in-plane lattice constant a. At least one III-nitride layer in the semiconductor structure has a bulk lattice constant aand [(|a&#x2212;a|)/a]100% is no more than 1%. A surface of the substrate opposite the surface on which the semiconductor structure is grown is textured.

In a III-nitride light emitting device, the device layers including the light emitting layer are grown over a template designed to reduce strain in the device, in particular in the light emitting layer. Reducing the strain in the light emitting device may improve the performance of the device. The template may expand the lattice constant in the light emitting layer over the range of lattice constants available from conventional growth templates. Strain is defined as follows: a given layer has a bulk lattice constant acorresponding to a lattice constant of a free standing material of a same composition as that layer and an in-plane lattice constant acorresponding to a lattice constant of that layer as grown in the structure. The amount of strain in a layer is |(a&#x2212;a)|/a. In some embodiments, the strain in the light emitting layer is less than 1%.

III-nitride light emitting devices grown on templates to reduce strain

A semiconductor structure includes a light emitting region, a p-type region disposed on a first side of the light emitting region, and an n-type region disposed on a second side of the light emitting region. At least 10% of a thickness of the semiconductor structure on the first side of the light emitting region comprises indium. Some examples of such a semiconductor light emitting device may be formed by growing an n-type region, growing a p-type region, and growing a light emitting layer disposed between the n-type region and the p-type region. The difference in temperature between the growth temperature of a part of the n-type region and the growth temperature of a part of the p-type region is at least 140&#xb0; C.

P-type layer for a III-nitride light emitting device

In a device, a III-nitride light emitting layer is disposed between an n-type region and a p-type region. A first spacer layer, which is disposed between the n-type region and the light emitting layer, is doped to a dopant concentration between 6&#xd7;10cmand 5&#xd7;10cm. A second spacer layer, which is disposed between the p-type region and the light emitting layer, is not intentionally doped or doped to a dopant concentration less than 6&#xd7;10cm.

III-nitride light emitting device with double heterostructure light emitting region

P-type layers of a GaN based light-emitting device are optimized for formation of Ohmic contact with metal. In a first embodiment, a p-type GaN transition layer with a resistivity greater than or equal to about 7 &#x3a9; cm is formed between a p-type conductivity layer and a metal contact. In a second embodiment, the p-type transition layer is any III-V semiconductor. In a third embodiment, the p-type transition layer is a superlattice. In a fourth embodiment, a single p-type layer of varying composition and varying concentration of dopant is formed.

Formation of Ohmic contacts in III-nitride light emitting devices

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Palo Alto, CA, United States of America

Werner K Goetz