Micron Technology Incorporated

Globalfoundries Inc.

Other

Nan Ya Technology Corporation

Werner Juengling

Kirk D Prall

Tyler A Lowrey

Guy T Blalock

Howard E Rhodes

Richard H Lane

Gurtej S Sandhu

Ravi T Iyer

Philip J Ireland

Pierre C Fazan

Pai-Hung Pan

Aftab A Ahmad

Kevin G Donohoe

Howard Kirsch

Sanh D Tang

John K Zahurak

Gordon A Haller

David J Keller

Ceredig Roberts

Trung Tri Doan

Kunal R Parekh

Charles L Ingalls

Min-Hwa Chi

Thomas Arthur Figura

Bipul C Paul

David S Becker

Steven M McDonald

Anurag Mittal

David L Dickerson

Steven D Cummings

Stephen M Krazit

Amy A Winder

William James Taylor, Jr

Viju K Mathews

Brent D Gilgen

Robert J Miller

Niladri Mojumder

Daniel T Pham

Paul Grisham

Sandeep Puri

Some embodiments include an integrated assembly having a base supporting first circuitry and first conductive lines. The first conductive lines extend along a first direction and are associated with the first circuitry. A deck is over the base and supports an array of memory cells and second conductive lines which are associated with the array of memory cells. The second conductive lines extend along a second direction which is substantially orthogonal to the first direction. Vertical interconnects extend from the deck to the base and couple the first conductive lines to the second conductive lines. Each of the vertical interconnects couples one of the first conductive lines to one of the second conductive lines. Each of the second conductive lines is coupled with only one of the first conductive lines.

Integrated assemblies comprising vertically-stacked decks with interconnected conductive lines

Some embodiments include an integrated assembly having a semiconductor-containing structure with a body region vertically between an upper region and a lower region. The upper region includes a first source/drain region. The lower region is split into two legs which are both joined to the body region. One of the legs includes a second source/drain region and the other of the legs includes a body contact region. The first and second source/drain regions are of a first conductivity type, and the body contact region is of a second conductivity type which is opposite to the first conductivity type. An insulative material is adjacent to the body region. A conductive gate is adjacent to the insulative material. A transistor includes the semiconductor-containing structure, the conductive gate and the insulative material. Some embodiments include methods of forming integrated assemblies.

Integrated assemblies having body contact regions proximate transistor body regions; and methods utilizing bowl etches during fabrication of integrated assemblies

A method of forming memory circuitry comprises using a digitline mask to form both: (a) conductive digitlines in a memory array area, and (b) lower portions of conductive vias in a peripheral circuitry area laterally of the memory array area. The lower portions of the vias electrically couple with circuitry below the vias and the digitlines. Pairs of conductive wordlines are formed above the digitlines in the memory array area. The pairs of wordlines extend from the memory array area into the peripheral circuitry area. Individual of the pairs are directly above individual of the lower portions of individual of the vias. Individual upper portions of the individual vias are formed. The individual upper portions both: (c) directly electrically couple to one of the individual lower portions of the individual vias, and (d) directly electrically couple together the wordlines of the individual pair of wordlines that are directly above the respective one individual lower portion of the respective individual via. Other methods, and structure independent of method of fabrication, are disclosed.

Memory circuitry and methods of forming memory circuitry

Integrated assemblies comprising vertically-stacked decks

Some embodiments include methods of forming integrated assemblies. First conductive structures are formed within an insulative support material and are spaced along a first pitch. Upper regions of the first conductive structures are removed to form first openings extending through the insulative support material and over lower regions of the first conductive structures. Outer lateral peripheries of the first openings are lined with spacer material. The spacer material is configured as tubes having second openings extending therethrough to the lower regions of the first conductive structures. Conductive interconnects are formed within the tubes. Second conductive structures are formed over the spacer material and the conductive interconnects. The second conductive structures are spaced along a second pitch, with the second pitch being less than the first pitch. Some embodiments include integrated assemblies.

Integrated assemblies

In some embodiments, a method used in forming an array of memory cells comprises uses no more than two photolithographic masking steps are used in forming both: (a) sense lines longitudinally extending in a column direction that are individually directly above and electrically coupled to the upper source/drain regions of multiple of the second pedestals in the column direction; and (b) spaced elevationally-extending vias laterally between immediately-adjacent of the sense lines directly above and electrically coupled to the upper source/drain regions of multiple of the first pedestals. Other embodiments are disclosed.

Methods used in forming an array of memory cells

Electronic apparatus, systems, and methods in a variety of applications can include a fin field effect transistor (FinFET) having a deposited fin body. Such a FinFET can be implemented as an access transistor in a circuit of an integrated circuit. In an embodiment, an array of FinFETs having a deposited fin bodies can be disposed on digitlines. For the array of FinFETs having a deposited fin bodies structured in memory cells of a memory, the digitlines can be coupled to sense amplifiers. Additional apparatus, systems, and methods are disclosed.

FinFETs with deposited fin bodies

In some embodiments, memory circuitry comprises a pair of immediately-adjacent memory arrays having space laterally there-between. The memory arrays individually comprise memory cells individually having upper and lower elevationally-extending transistors and a capacitor elevationally there-between. The memory arrays comprise individual rows that (a) have an upper access line above and directly electrically coupled to a lower access line, and (b) are directly electrically coupled to one another across the space. The lower access line in one of the rows extends across the space from one of the memory arrays to the other of the memory arrays. Another of the rows comprises a conductive interconnect extending across a portion of the space. The conductive interconnect includes a horizontally-extending portion within the space that is laterally offset from the another row. Other aspects and implementations are disclosed.

Memory circuitry having a pair of immediately-adjacent memory arrays having space laterally-there-between that has a conductive interconnect in the space

Integrated assemblies comprising vertically-stacked decks of memory arrays

Some embodiments include an integrated assembly having a conductive line supported by a deck and extending along a longitudinal direction. The conductive line is configured to carry an electrical signal. A connection region is along the conductive line. The conductive line splits amongst multiple components as it passes through the connection region. The components are spread-apart from one another along a lateral direction which is orthogonal to the longitudinal direction. An opening extends vertically through the deck and through the connection region. The opening breaks one of the components of the conductive line to leave another of the components to carry the electrical signal across the connection region.

Integrated assemblies comprising redundant wiring routes, and integrated circuit decks having openings extending therethrough

An apparatus comprises a base structure, a memory structure, and interconnect structures. The base structure comprises odd sense amplifiers and even sense amplifiers. The memory structure comprises 3D memory arrays having decks each comprising digit lines, additional digit lines, memory cells, and word lines. The digit lines comprise odd digit lines and even digit lines, and the additional digit lines comprise additional odd digit lines and additional even digit lines. The memory cells are connected to the digit lines and the additional digit lines, and each comprise two transistors and one capacitor. The word lines are connected to the memory cells, and comprise odd word lines and even word lines. The interconnect structures comprise odd interconnect structures connecting the odd sense amplifiers to the odd digit lines and the additional odd digit lines, and even interconnect structures connecting the even sense amplifiers to the even digit lines and the additional even digit lines. Related electronic systems and methods are also described.

Apparatuses including 3D memory arrays, methods of forming the apparatuses, and related electronic systems

Some embodiments include a memory array which has rows of fins. Each fin has a first pedestal, a second pedestal and a trough between the first and second pedestals. A first source/drain region is within the first pedestal, a second source/drain region is within the second pedestal, and a channel region is along the trough between the first and second pedestals. Digit lines are electrically coupled with the first source/drain regions. Ferroelectric capacitors are electrically coupled with the second source/drain regions. Wordlines are along the rows of fins and overlap the channel regions. Conductive isolation lines are under the wordlines along the rows of fins.

Memory arrays comprising ferroelectric capacitors

Growing community of inventors

Boise, ID, United States of America

Werner Juengling