Infineon Technologies Ag

Werner Ertle

Bernd Goller

Michael Horn

Wolfgang Stadler

Oliver Nagler

Robert Bauer

Bernd Kothe

Reinhard Greiderer

Olaf Schmeckebier

Till Frohnmüller

The invention relates to an arrangement of contact areas and test areas on patterned semiconductor chips. The contact areas and the test areas are electrically connected to one another via a conduction web. Whereas the contact areas are arranged in a first region, which has no components of an integrated circuit, the test areas lie in a second region of the top side of the semiconductor chip, which region has components of an integrated circuit.

Semiconductor wafer with electrically connected contact and test areas

An integrated semiconductor structure has a substrate, a semiconductor element located on the substrate, a pad metal, metal layers located between the pad metal and the substrate, and insulation layers that separate the metal layers from one another. The pad metal extends over at least&#x2014;part of the semiconductor element. Below the surface of the pad metal, at least the top two metal layers include two or more adjacent interconnects.

Semiconductor structure integrated under a pad

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Neubiberg, Germany

Werner Ertle