Alcatel

Alcatel Lucent

Alcatel N.v.

Werner Beisel

Michael Joachim Wolf

Pierre A Humblet

Kalman Szechenyi

Christian Hermsmeyer

Geoffrey Dive

Hans-Jörg Jäkel

Hartmut Borschel

Albrecht Schaffert

J&uuml;rgen Kasper

J&uuml;rgen H&ouml;hn

Wolfgang Krips

Brian William Schoenherr

David Scheer

Joerg Pleickhardt

Albert Norz

Jörg Pleickhardt

In order to provide a network element for switching time-division multiplex signals in a transport network, which allows higher capacity at moderate equipment costs, the network element has a number of input ports (I; IO-IO), a number of output ports (O; IO-IO) and a switch fabric ( ) SF;) interconnecting the input and output ports (IO-IO). The switching fabric ( ) SF;) is a cell based switch comprising one or more switch modules ( ) SE-SEn) which are adapted to switch fixed-length cells on the basis of addresses contained in cell headers of the cells. The input ports (I) contain a segmentation device () for segmenting an input time-division multiplex signal into fixed-length cells and assigning address information to each cell. The output ports (O) contain a reassembly device () for reassembling cells received from said switch fabric (SF;) into an output time-division multiplex signal. The address information contains a fabric address (H, H) and a TDM address (P, P). The switch fabric switches the cells in accordance with the fabric address (H, H) to a corresponding output port (O) and the reassembly device () reassembles the cells in accordance with the TDM address (P, P).

Network element for switching time division multiplex signals

A network element for a transport network contains a multistage lower order switching matrix with at least an input matrix stage and an output matrix stage designed to switch lower order multiplex units and with a center stage capable of switching higher order multiplex units, only, thereby connecting the input and output stages.

Network element with multistage lower order switching matrix

A network element with equipment protection has first and second redundant signal paths for first and second redundant signals; a selector for selecting either of the two redundant signals as active; and first and second transition monitors coupled to the first and second signal paths, respectively, for monitoring the first and second signals for bit level transitions. The selector is controlled by the transition monitors to alter selection in the case that the selected signal does not contain bit level transitions while the non-selected signal does.

Hitless protection switching

A network device (NWE) for a digital transmission network with synchronous digital hierarchy receives data steams containing frames with data packets mapped therein and addressed by a phase reference identifier. Internally, the network device has redundant transfer paths which potentially cause different delay. The network element compensates for that delay by adjusting the phase reference identifier allocated to a respective data packet by a predetermined phase correcting value, leading in the phase, which corresponds to a maximum expected delay for transfer of the data packets on internal transfer paths, and by buffering the data packet by a buffering time such that its buffering time and its delay actually needed for passing through the network device in total correspond to the maximum expected delay taken into account by the phase adjustment.

Network device and method for delay compensation of data packets

A method of synchronizing at least one receiver module (MOD , MOD ), in particular a receiver module in a telecommunications network or in a network device of a telecommunications network, has the following steps: A first clock signal (TS ) and a second clock signal (TS ) are sent to the at least one receiver module (MOD , MOD ). In addition, at least one item of master-slave-status information (MSX) about the at least one first clock signal (TS ) and/or the second clock signal (TS ) is sent to the at least one receiver module (MOD , MOD ). Based on the item of master-slave-status information (MSX), the at least one receiver module (MOD , MOD ) selects the first clock signal (TS ) or the second clock signal (TS ) as master synchronization signal for its synchronization.

Method, clock generator module and receiver module for synchronizing a receiver module

A synchronous transmission system is disclosed in which the transmission paths (leased lines) extend over several individual transmission systems (Sx). Monitoring devices (NIM) with access to at least one byte of the control data area are provided in synchronous transmission systems to write data into or read data out of the control data area. The monitoring devices (NIM) may thus be controlled and monitored by a signal source (S ).

Synchronous transmission system with fault location function and monitoring device therefor

The invention concerns a network element and an input-output unit (,) for a synchronous transmission system according to the standard for Synchronous Digital Hierarchy or according to the comparable Synchronous Optical Network (SONET) standard. The input-output unit (,) contains a signal processing device (,) that has a reception data memory (,), a transmission data memory (,), a control unit (,) and a processor (,). The processor (,) is a digital signal processor which essentially carries out the processing of a STM-N signal.

Network element and input/output device for a synchronous transmission system

In a data transmission system, a switching network in a connection node (VK) includes switch groups (SCH) for switching channels, which are each assigned to one or more time slots within the framework of a multiplex time signal, e.g. virtual containers of a STM-1 frame according to CCITT recommendations G707 to G.709. Each switch group (SCH) is modular and linked to one another, and contains a memory (DS) with several independently readable memory outputs (SA1 to SA4), through which the storage area can be accessed. Each part signal of a respective memory address can be connected with a data output of the switch group (SCH) through selectors (SEL1 to SEL4). A connecting memory (VB1 to VB4) controls the reading of each part signal from the memory (DS) to a memory output (SA1 to SA4) and a selector (SEL1 to SEL4). A coupling field may be composed of switch groups (SCH) arranged in columns and lines, as required. Each data outputs (DA1 to DA4) of one switch group (SCH MN) is connected to a connection input (VE1 to VE4) of the following switch group.

Switching network for switching channels

The network access node of a digital communication system for the bidirectional transmission of message signals between, for example, a switching center and subscribers as an electrically switchable connection between the lines to the switching centers with a first interface and the lines to the subscribers with a second interface. The first interface is preferably an interface for a time-division multiplex signal with a transmission rate of 2 Mbit/s; the second interface is preferably an interface for signals in multiple access with time-division multiplex (TDM/TDMA). The buffer memory of the TDM/TDMA system is made up of partial memories arranged as a matrix. The partial memories are used simultaneously as a buffer memory for the circuit of the paths.

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Ludwigsburg, Germany

Werner Beisel