International Business Machines Corporation

Kabushiki Kaisha Toshiba

Advanced Micro Devices Corporation

Globalfoundries Inc.

Werner A Rausch

Huajie Chen

Huilong Zhu

Ghavam G Shahidi

Rajiv V Joshi

Randy William Mann

Subhash Balakrishna Kulkarni

Bruce Bennett Doris

Dureseti Chidambarrao

Rasit Onur Topaloglu

Henry K Utomo

Sadanand Vinayak Deshpande

Effendi Leobandung

Oleg Gluschenkov

Chengwen Pei

Dominic Joseph Schepis

Shreesh Narasimha

Omer H Dokumaci

Sami Rosenblatt

James A Culp

Fariborz Assaderaghi

Jared Barney Hertzberg

Siddhartha Panda

Luigi Ternullo, Jr

Eric Adler

Sang-Hyun Oh

Edward J Nowak

Steven H Voldman

Haining S Yang

Terence B Hook

Geng Wang

Tsutomu Sato

Wilfried Haensch

Bomy A Chen

James Albert Slinkman

Louis C Hsu

K Paul Muller

Karen A Nummy

Francis Roger White

Christopher D Sheraw

Bijan Davari

Tina Jane Wagner

Jawahar P Nayak

David M Onsongo

Melanie J Sherony

Noah D Zamdmer

William R Dachtera

Alyssa C Bonnoit

Kangguo Cheng

Ali Khakifirooz

Juntao Li

Jack Allan Mandelman

Louis L Hsu

Kevin K Chan

Ying Di Zhang

Judson Robert Holt

Michael Patrick Chudzik

Qingqing Liang

Brian Joseph Greene

Renee Tong Mo

Thomas W Dyer

Gregory Gower Freeman

Jerome Brett Lasky

Nivo Rovedo

Edward P Maciejewski

Dan Moy

Ying Li

Anda C Mocuta

Mahender Kumar

Atul Champaklal Ajmera

Jian Yu

Dan Mihai Mocuta

Michael Abramovich Gribelyuk

Paul Andrew Ronsheim

Woo-Hyeong Lee

Kevin McStay

Hasan Munir Nayfeh

Ning Su

Heemyong Park

Leon Stok

Ralph W Young

Ryan Matthew Mitchell

Robin Van Den Nieuwenhuizen

Jerome Bret Lasky

Sang-Hyun c/o Ibm United Kingdom Ltd Oh

Tsutomu Ibm United Kingdom Ltd Sato

Huajie Ibm United Kingdom Ltd Chen

Henry K c/o Ibm United Kingdom Ltd Utomo

David M c/o Ibm United Kingdom Limited Onsongo

Methods and systems for a circuit similarity metric for semiconductor testsite coverage. One or more unique values for each of a set of measures for each circuit layout of a plurality of circuit layouts are identified and a pairwise comparison across the set of measures is conducted for a selected pair of the plurality of circuit layouts to derive a similarity score for the selected pair of circuit layouts. The similarity score is incremented for the selected pair in response to the selected pair of circuit layouts sharing a same unique value and the similarity score is decremented for the selected pair in response to one circuit layout of the selected pair of circuit layouts having a unique value that the other circuit layout of the selected pair does not contain.

Circuit layout similarity metric for semiconductor testsite coverage

A vertical q-capacitor includes a trench in a substrate through a layer of superconducting material. A superconductor is deposited in the trench forming a first film on a first surface, a second film on a second surface, and a third film of the superconductor on a third surface of the trench. The first and second surfaces are substantially parallel, and the third surface in the trench separates the first and second surfaces. A dielectric is exposed below the third film by etching. A first coupling is formed between the first film and a first contact, and a second coupling is formed between the second film and a second contact in a superconducting quantum logic circuit. The first and second couplings cause the first and second films to operate as the vertical q-capacitor that maintains integrity of data in the superconducting quantum logic circuit within a threshold level.

Vertical superconducting capacitors for transmon qubits

An eFuse device on a substrate is formed on a substrate used for an integrated circuit. A semiconductor structure is created from a semiconductor layer deposited over the substrate. A mask layer is patterned over the semiconductor structure such that a first region of the semiconductor structure is exposed and a second region of the semiconductor structure is protected by the mask layer. Next, a self-limiting etch is performed on the exposed areas in the first region of the semiconductor structure, producing a first faceted region of the semiconductor structure in the first region. The semiconductor in the first faceted region has a minimum, nonzero thickness at a point where two semiconductor facet planes meet which is thinner than a thickness of semiconductor in the second region of the semiconductor structure is protected by the mask layer. The first faceted region is used as a link structure in the eFuse device.

Faceted structure formed by self-limiting etch

A semiconductor device such as a FinFET includes a plurality of fins formed upon a substrate and a gate covering a portion of the fins. Diamond-shaped volumes are formed on the sidewalls of the fins by epitaxial growth which may be limited to avoid merging of the volumes or where the epitaxy volumes have merged. Because of the difficulties in managing merging of the diamond-shaped volumes, a controlled merger of the diamond-shaped volumes includes depositing an amorphous semiconductor material upon the diamond-shaped volumes and a crystallization process to crystallize the deposited semiconductor material on the diamond-shaped volumes to fabricate controllable and uniformly merged source drain.

Merged source drain epitaxy

A trench is formed in a semiconductor substrate, and is filled with a node dielectric layer and at least one conductive material fill portion that functions as an inner electrode. The at least one conductive material fill portion includes a doped polycrystalline semiconductor fill portion. A gate stack for an access transistor is formed on the semiconductor substrate, and a gate spacer is formed around the gate stack. A source/drain trench is formed between an outer sidewall of the gate spacer and a sidewall of the doped polycrystalline semiconductor fill portion. An epitaxial source region and a polycrystalline semiconductor material portion are simultaneously formed by a selective epitaxy process such that the epitaxial source region and the polycrystalline semiconductor material portion contact each other without a gap therebetween. The polycrystalline semiconductor material portion provides a robust low resistance conductive path between the source region and the inner electrode.

Low resistance embedded strap for a trench capacitor

Disclosed is an SOI device on a bulk silicon layer which has an FET region, a body contact region and an STI region. The FET region is made of an SOI layer and an overlying gate. The STI region includes a first STI layer separating the SOI device from an adjacent SOI device. The body contact region includes an extension of the SOI layer, a second STI layer on the extension and a body contact in contact with the extension. The first and second STI layers are contiguous and of different thicknesses so as to form a split level STI.

Split level shallow trench isolation for area efficient body contacts in SOI MOSFETS

The present invention provides an improved CMOS diode structure with dual gate conductors. Specifically, a substrate comprising a first n-doped region and a second p-doped region is formed. A third region of either n-type or p-type conductivity is located between the first and second regions. A first gate conductor of n-type conductivity and a second gate conductor of p-type conductivity are located over the substrate and adjacent to the first and second regions, respectively. Further, the second gate conductor is spaced apart and isolated from the first gate conductor by a dielectric isolation structure. An accumulation region with an underlying depletion region can be formed in such a diode structure between the third region and the second or the first region, and such an accumulation region preferably has a width that is positively correlated with that of the second or the first gate conductor.

CMOS diodes with dual gate conductors, and methods for forming the same

A method of forming a field effect transistor creates shallower and sharper junctions, while maximizing dopant activation in processes that are consistent with current manufacturing techniques. More specifically, the invention increases the oxygen content of the top surface of a silicon substrate. The top surface of the silicon substrate is preferably cleaned before increasing the oxygen content of the top surface of the silicon substrate. The oxygen content of the top surface of the silicon substrate is higher than other portions of the silicon substrate, but below an amount that would prevent epitaxial growth. This allows the invention to epitaxially grow a silicon layer on the top surface of the silicon substrate. Further, the increased oxygen content substantially limits dopants within the epitaxial silicon layer from moving into the silicon substrate.

Ultra shallow junction formation by epitaxial interface limited diffusion

The present invention provides a method of forming asymmetric field-effect-transistors. The method includes forming at least a first and a second gate-mask stack on top of a semiconductor substrate, wherein the first and second gate-mask stacks include at least, respectively, a first and a second gate conductor of a first and a second transistor and have, respectively, a top surface, a first side, and a second side with the second side being opposite to the first side; performing a first halo implantation from the first side of the first and second gate-mask stacks at a first angle while applying the first gate-mask stack in preventing the first halo implantation from reaching a first source/drain region of the second transistor, wherein the first angle is equal to or larger than a predetermined value; and performing a second halo implantation from the second side of the first and second gate-mask stacks at a second angle, thereby creating halo implant in a second source/drain region of the second transistor, wherein the first and second angles are measured against a normal to the substrate.

Method of creating asymmetric field-effect-transistors

A semiconductor structure including at least one transistor is provided which has a stressed channel region that is a result of having a stressed layer present atop a gate conductor that includes a stack comprising a bottom polysilicon (polySi) layer and a top metal semiconductor alloy (i.e., metal silicide) layer. The stressed layer is self-aligned to the gate conductor. The inventive structure also has a reduced external parasitic S/D resistance as a result of having a metallic contact located atop source/drain regions that include a surface region comprised of a metal semiconductor alloy. The metallic contact is self-aligned to the gate conductor.

Structure and method for fabricating self-aligned metal contacts

The present invention, in one embodiment, provides a memory device including a substrate including at least one device region; a first field effect transistor having a first threshold voltage and a second field effect transistor having a second threshold voltage, the second field effect transistor including a second active region present in the at least one device region of the substrate, the second active region including a second drain and a second source separated by a second channel region, wherein the second channel region includes a second trap that stores holes produced when the first field effect transistor is in the on state, wherein the holes stored in the second trap increase the second threshold voltage to be greater than the first threshold voltage.

2-T SRAM cell structure and method

Growing community of inventors

Stormville, NY, United States of America

Werner A Rausch