Freescale Semiconductor,inc.

Nxp Usa, Inc.

Wenzhong Zhang

Michael A Stockinger

Shayan Zhang

Chris C Dao

Yi Zhao

Xu Zhang

Stefano Pietri

Jehoda Refaeli

Liang Qiu

Jose A Camarena

Yin Guo

Rishi Bhooshan

Ajay Kumar Sharma

Area and routing overhead issues of traditional anamux incorporation in a semiconductor device are overcome by placing a functional anamux block on top of an I/O pad. In some embodiments, multiple anamux blocks can be stacked either vertically or placed on neighboring I/O pads for horizontal stacking. Embodiments provide the anamux blocks as the same width as the I/O pads and the width is optimized to minimize padring height. In some embodiments, a power/ground I/O (PGE) bond pad architecture is enabled by the incorporation of both I/O pad and anamux blocks in the same region, providing two bonding regions, which can further reduce chip area. Some embodiments also permit routing of signals through the anamux block to neighboring blocks and the I/O channels.

Integrated input/output pad and analog multiplexer architecture

A multi-branch analog multiplexer (anamux) includes protection circuitry to help dissipate both positive and negative injected current without increasing the size of hardening transistors in each branch, thereby avoiding increased leakage current and enabling an analog to digital converter to operate with the required accuracy. The protection circuitry is tied to the body of the hardening transistor to lower the threshold voltage of the hardening device, thereby enabling the hardening device to handle more of the injected current.

Analog multiplexer with current injection protection

A transmission gate circuit includes a pass gate and a control circuit and provides High Voltage protection to a flash memory in a characterization mode and a low resistive path with true open-drain functionality in a normal mode. A native NMOSFET in series with the pass gate provides overvoltage protection for additional circuitry. Well biasing, gate tracking and internal node clamping circuits ensure that all of the devices of the pass gate and control circuit operated within safe operational voltage levels. The two modes of operation can be selected by an enable signal. The transmission gate circuit can support up to a 5.5 volts input in a true open drain mode while an input/output supply voltage of 3.3 volts is supplied.

Transmission gate circuit

A voltage level shifter for high voltage applications has a low voltage domain current mirror having first and second branches. A high voltage switch and a resistor are connected in series with the second branch. An output stage provides an output signal that is a function of a voltage difference across the resistor, and the output stage and the resistor are in the high voltage domain. Assertion of an input signal in the low voltage domain develops a first current in the first branch, and causes the high voltage switch to pass in the resistor a second current from the second branch that is a function of the first current and develops the voltage difference across the resistor. Only the high voltage switch needs to have high breakdown voltage characteristics.

Voltage level shifter for high voltage applications

An integrated circuit electrical protection device is disclosed that includes a semiconductor substrate and a plurality of transistor fingers partitioned into a plurality of segments. The segments are distinguished from one another by well-ties spaced apart from each other within a source/drain region that is shared by adjacent segments.

Integrated circuit electrical protection device

An amplifier applies a self-adapting voltage to an output terminal. A bias circuit provides a greater bias current in a first external connection condition, in the absence of a pull-up resistance connected to the output terminal, than when such a pull-up resistance is present. The amplifier applies a different voltage to the output terminal in the absence of a pull-up resistance than when such a pull-up resistance is present. The circuit can be used in a portable device for receiving charging current from a battery charger through a connector having a D+ pin for connection to the battery charger and connected to the amplifier output terminal for battery charger detection. The portable device can meet the USB battery charger specification rev. 1.2.

Self-adapting voltage amplifier and battery charger detection

A comparator used in a clock signal generation circuit compares two input signals and generates an output signal. The comparator has first and second input transistors coupled to the input signals. First and second hysteresis transistors are coupled between the input transistors and an output stage of the comparator, and apply hysteresis to a comparison of the input signals. First and second hysteresis control transistors are coupled between the input transistors and the hysteresis transistors to isolate the hysteresis transistors from the input transistors under control of a hysteresis enable signal. The comparator is operable in a first mode or a second mode based on a hysteresis enable signal. In the first mode the comparator applies hysteresis to the comparison of the input signals and in the second mode, compares the input signals without hysteresis.

Comparator and clock signal generation circuit

A voltage level shifter has an input circuit with an inverter coupled to an input node, a pull-down control transistor with a gate coupled to a first node of the inverter, and a pull-up control transistor with a gate coupled to a second node of the inverter. Sources of the pull-down and pull-up control transistors are coupled to a low voltage reference. A transient connectivity limiter (TCL) has pull-down and pull-up transistors. Two control inputs are coupled to respective first and second nodes of the inverter and path inputs are coupled to respective drains of the pull-down and pull-up control transistors. An output circuit has inputs coupled to pull-up and pull-down nodes of the TCL. During a voltage level transition at the input node, the TCL connects the pull-up node to the low voltage reference through the TCL pull-up transistor transitioning from a saturation to a sub-threshold region of operation.

Voltage level shifter

A transmission gate circuit includes a first transmission gate, having a first switching device, coupled in series with a second transmission gate, having a second switching device, and control circuitry which places the first transmission gate and the second transmission gate into a conductive state to provide a conductive path through the first transmission gate and the second transmission gate. When the voltage of the first terminal is above a first voltage level and outside a safe operating voltage area of at least one of the first and second switching device, the first switching device remains within its safe operating voltage area and the second switching device remains within its safe operating voltage area.

Transmission gate circuitry for high voltage terminal

An oscillator circuit has a crystal oscillator amplifier having only two clock input terminals, one being an input terminal and the other being an output terminal. The input terminal allows a user of the integrated circuit to choose between connecting a first clock signal generated from a crystal or a second clock signal generated by a non-crystal source to the input terminal. Control circuitry has a capacitor coupled in parallel with a transistor. Both are coupled in series with a resistive device at an output of the control circuitry to provide a control signal. Clock generation circuitry coupled to the crystal oscillator amplifier provides an oscillating output signal in response to an enable signal. In one form a comparator circuit provides the oscillating output signal. The control signal is used to ensure that inputs to the comparator circuit repeatedly cross each other over time.

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Tianjin, China

Wenzhong Zhang