Chartered Semiconductor Manufacturing Ltd (corporation)

International Business Machines Corporation

Samsung Electronics Co., Ltd.

Wenzhi Gao

Young Way Teh

Xiangdong Chen

Christopher V Baiocco

Huang Liu

Elgin Kiok Boone Quek

Jae Gon Lee

Chung Woh Lai

Atul Champaklal Ajmera

Johnny Widodo

Zhao Lun

Liang-Choo Hsia

Shailendra Mishra

Alex K H See

Young Gun Ko

James Yongmeng Lee

Process for enhancing strain in a channel with a stress liner, spacer, process for forming integrated circuit and integrated circuit. A first spacer composed of an first oxide and first nitride layer is applied to a gate electrode on a substrate, and a second spacer composed of a second oxide and second nitride layer is applied. Deep implanting of source and drain in the substrate occurs, and removal of the second nitride, second oxide, and first nitride layers.

Spacer and process to enhance the strain in the channel with stress liner

An integrated circuit system that includes: providing a substrate including an active device with a gate and a gate dielectric; forming a first liner, a first spacer, a second liner, and a second spacer adjacent the gate; forming a material layer over the integrated circuit system; forming an opening between the material layer and the first spacer by removing a portion of the material layer, the second spacer, and the second liner to expose the substrate; and forming a source/drain extension and a halo region through the opening.

Integrated circuit system for suppressing short channel effects

An integrated circuit system that includes: providing a substrate; depositing a dielectric on the substrate; depositing an isolation dielectric on the dielectric; forming a trench through the isolation dielectric and the dielectric to expose the substrate; depositing a dielectric liner over the integrated circuit system; processing the dielectric liner to form a trench spacer; and depositing an epitaxial growth within the trench that includes a crystalline orientation that is substantially identical to the substrate.

Integrated circuit system employing selective epitaxial growth technology

An improved method for applying stress proximity technique process on a semiconductor device and the improved device is disclosed. In one embodiment, the method utilizes an additional set of sidewall spacers on one or more NFET devices during the fabrication process. This protects the one or more of the NFET devices during the activation of a compressive PFET stress liner, thereby reducing the compressive forces on the one or more NFET devices, and creating a semiconductor device with improved performance.

Method for improved fabrication of a semiconductor using a stress proximity technique process

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Singapore, Singapore

Wenzhi Gao