Yangtze Memory Technologies Co., Ltd.

Yangzte Memory Technologies., Ltd.

Wenzhe Wei

Hongtao Liu

Ying Huang

Dejia Huang

Song Min Jiang

Qiguang Wang

Yali Song

Kaikai You

Da Li

Feng Xu

Ming Wang

A memory device includes a memory array including memory strings and a first word line, and a peripheral circuit coupled to the memory array. Each memory string includes a select gate transistor and memory cells. The peripheral circuit is configured to apply, during a first time period, a program voltage to the first word line to program a first memory cell in a selected memory string, apply, during a second time period after the first time period, a first verify voltage to the first word line to verify the first memory cell, compare the first verify voltage with a target voltage to obtain a comparing result, and in response to the comparing result indicative of the first verify voltage being higher than the target voltage, turn off, during a third time period between the first and the second time periods, the select gate transistor in an unselected memory string.

Memory device and program operation thereof

A memory includes wordline (WL) layers and a controller coupled to the WL layers. The controller is configured to apply at least one verify voltage to a first WL layer of the WL layers during a verify phase, and apply a first pass voltage to a second WL layer of the WL layers during the verify phase. A first memory cell of the first WL layer is programmed before a second memory cell of the second WL layer. The first pass voltage is higher than a threshold voltage of a memory cell in a lowest programming state.

3D NAND flash and operation method thereof

A method of programming a memory device including a cell is provided. A first program pulse is applied to the cell. Middle program pulses are applied to the cell after the application of the first program pulse. A last program pulse is applied to the cell after the application of the middle program pulses. A pulse width of the last program pulse is wider than a pulse width of each of the middle program pulses and the first program pulse.

Control method and controller of 3D NAND flash

A programming method for a memory device is disclosed. The programming method comprises moving a plurality of first charge carriers at a shallow energy level to a channel in a substrate layer before a programming operation for a first word line, wherein the plurality of first charge carriers at the shallow energy level correspond to a memory cell to be programmed.

Memory device and programming method thereof

In certain aspects, a memory device includes memory strings each including a drain select gate (DSG) transistor and memory cells, and a peripheral circuit coupled to the memory strings. The peripheral circuit is configured to, in a program/verify cycle, program a target memory cell of the memory cells in a select memory string of the memory strings, and after programming the target memory cell, verify the target memory cell using one or more verify voltages including an initial verify voltage. The peripheral circuit is also configured to compare the initial verify voltage with a threshold verify voltage so as to obtain a comparing result, and control, at least based on the comparing result, the DSG transistor in an unselect memory string of the memory strings between programming and verifying the targe memory cell.

NAND flash memory device and method of reducing program disturb thereof

A memory device includes a memory array including a cell, and a controller coupled to the memory array. The controller is configured to control sequentially applying programming voltage pulses to the cell. A pulse width of each of the programming voltage pulses decreases as a pulse count of the programming voltage pulses increases.

An operation method for a 3D NAND flash including a plurality of wordline (WL) layers. The operation method includes: writing data into a WLn layer of the plurality of WL layers according to a writing sequence from a first end of the plurality of WL layers to a second end of the plurality of WL layers in a write operation, wherein the WLn layer is a selected WL layer; and applying a first pass voltage on a first WL layer of the plurality of WL layers and applying a second pass voltage on a second WL layer of the plurality of WL layers during a verify phase; wherein the operation method is operated without a pre-pulse phase during or before the verify phase.

A programming method for a memory device is disclosed. The programming method comprises moving a plurality of first charge carriers at a shallow energy level to a channel in a substrate layer before a fine programming operation for a first word line, wherein the plurality of first charge carriers at the shallow energy level correspond to a memory cell to be programmed.

An operation method for a 3D NAND flash includes writing data into a WLn layer of the plurality of wordline layers of an unselect bit line of the plurality of bit lines in a write operation; and applying a first pass voltage on at least a first WL layer of the plurality of wordline layers of the unselect bit line of the plurality of bit lines and applying a second pass voltage on at least a second WL layer of the plurality of wordline layers of the unselect bit line of the plurality of bit lines; wherein the operation method is operated when a pre-pulse phase is removed from a verify phase.

An operating method and a non-volatile memory device are provided. The non-volatile memory device includes a memory array including a plurality of memory cells. The operating method includes applying a first program voltage signal to selected word lines connected to selected memory cells during a first program period and measuring a first threshold voltage, applying a second program voltage signal to the selected word lines during a second program period and measuring a second threshold voltage, applying a test bit line voltage signal to selected bit lines and applying a third program voltage signal to the selected word lines during a third program period and measuring a third threshold voltage and determining the enhanced bit line voltage by comparing a difference between the third threshold voltage and the second threshold voltage with a difference between the second threshold voltage and the first threshold voltage.

Operating method of generating enhanced bit line voltage and non-volatile memory device

In a memory device which includes a plurality of memory cells, a top dummy storage region, a bottom dummy storage region, a plurality of word lines and a plurality of bit lines form in a substrate, a selected bit line among the plurality of bit lines, a channel region in the substrate and a source region in the substrate are pre-charged and a negative pre-pulse voltage is applied to the bottom dummy storage region during a first period. A selected memory cell among the plurality of memory cells is programmed during a second period subsequent to the first period, wherein the selected memory cell is coupled to the selected bit line and a selected word line among the plurality of word lines.

Method of programming memory device and related memory device

A control method of a programming process for a three-dimensional (3D) NAND flash memory array comprises programming a bit-cell of the 3D NAND flash memory array in a programming stage; and verifying whether the bit-cell of the 3D NAND flash memory array is programmed in a verification stage after the programming stage; wherein the programming stage comprises programming the bit-cell of the 3D NAND flash memory array with a plurality of programming voltage pulses; wherein the verification stage comprises reading the bit-cell of the 3D NAND flash memory array with lower or higher voltage than normal reading voltage pulse.

Control method and controller of a programming process for 3D NAND flash

A programming method of an increment step pulse program (ISPP) for a three-dimension (3D) NAND flash includes programming a select wordline of an unselect bit line of the 3D NAND flash; performing a first verification process with at least a verification voltage on the select wordline; determining whether a first verification voltage of the first verification process for the select wordline is higher than a default voltage or not; and removing a pre-pulse phase of the ISPP when the first verification voltage is higher than the default voltage; wherein the first verification voltage is a following verification voltage of the first verification process.

An operation method for a 3D NAND flash includes writing data into a WLn layer of the plurality of wordline layers of an unselect bit line of the plurality of bit lines in a write operation; and applying a first pass voltage on at least a first WL layer of the plurality of wordline layers of the unselect bit line of the plurality of bit lines and applying a second pass voltage on at least a second WL layer of the plurality of wordline layers of the unselect bit line of the plurality of bit lines; wherein the first pass voltage is lower than the second pass voltage to reduce a difference of channel potential between the WLn layer and the at least a first WL layer when a pre-pulse phase is removed from a verify phase.

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Wuhan, China

Wenzhe Wei