Semiconductor Manufacturing International (shanghai) Corporation

Semiconductor Manufacturing International (beijing) Corporation

Wenzhe Luo

Paul Ouyang

Feng Chen

Qingyang Wu

Jiaqing Wang

Yunxiang Peng

A demodulation circuit for an Amplitude Shift Keyed (ASK) modulated signal includes an envelope detector, an alternating voltage amplifier, a differentiator circuit, and a comparator having a hysteresis connected in series. The envelope detector produces an envelope signal from the received ASK signal. The amplifier blocks the DC component of the envelope signal and amplifies AC components of the envelope signal to obtain a steeper slope of the rising and falling edges. The differentiator circuit then processes the transition edges to provide a differentiated signal having positive and negative electrical pulses. The comparator converts the pulses into a binary data stream which corresponds to the transmitted data stream. The combination of the differentiated signal and comparator having a hysteresis enables better stability and sensitivity of the ASK demodulation circuit.

Amplitude shift keyed (ASK) demodulation pattern and use in radio frequency identification (RFID)

A flash memory system includes a first flash memory cell having a first floating gate, a first source region, and a first control gate. The first control gate is connected to a word line. The first flash memory cell includes a first oxide layer separating the first control gate from the first floating gate and a first drain region connecting to a first bit line. The flash memory system also includes a second flash memory cell having a second floating gate, a second source region, and a second control gate. The second control gate is connected to the word line. The second flash memory cell includes a second oxide layer separating the second control gate from the second floating gate and a second drain region connecting to a second bit line. A comparator processes a first and second input signals received from the respective first and second bit lines.

Method of flash memory design with differential cell for better endurance

A method of programming a differential flash memory cell having a first and a second memory cell is disclosed. The first memory cell includes a first transistor associated with a first threshold voltage and the second memory cell includes a second transistor associated with a second threshold voltage. The method includes reading the first and second memory cells to determine a current associated with the first and second threshold voltages. The first threshold voltage is equal to a first value and the second threshold voltage is equal to a second value. The method further includes determining if the first current corresponds to a predetermined logic state. If the current does not correspond to the predetermined logic state, the first and second memory cells are programmed. The programming includes changing the first threshold voltage from the first value to a third value and the second threshold voltage from the second value to a fourth value.

Method of programming flash memory of the differential cell structures for better endurance

A system and method for sensing a current. The system includes an operational amplifier including a first input terminal, a second input terminal, and a first output terminal. The first input terminal is biased to a predetermined voltage, and the second input terminal and the first output terminal are directly connected. Additionally, the system includes a switch coupled to the first output terminal and a first node. The switch is controlled by at least a first control signal. Moreover, the system includes a comparator including a third input terminal, a fourth input terminal, and at least a second output terminal. The comparator is configured to receive a first input signal at the third input terminal and a second input signal at the fourth input terminal. The first input signal and the second input signal are associated with the first node and the predetermined voltage.

High performance sense amplifier and method thereof for memory system

An apparatus and method for providing a reference voltage for regulating voltage levels. The apparatus includes a first voltage generation system for receiving a first control signal and output a calibration voltage, a voltage adjustment system for receiving the calibration voltage and a reference voltage and output a second control signal, and a second voltage generation system for receiving the second control signal and output the reference voltage. The voltage adjustment system includes a latch system for receiving a third control signal and a fourth control signal and output the first control signal.

Device and method for voltage regulator with low standby current

An apparatus and method for regulating voltage levels. The apparatus includes a first transistor and a second transistor. The first transistor and the second transistor are each coupled to a first current source and a second current source. Additionally, the apparatus includes a third transistor coupled to the second transistor and configured to receive a first voltage from the second transistor, and a fourth transistor configured to receive the first voltage from the second transistor and generate an output voltage. Moreover, the apparatus includes an adaptive system coupled to the fourth transistor. Also, the apparatus includes a delay system coupled to the third transistor and configured to receive a sensing current from the third transistor and generate a delayed current associated with a predetermined time delay. Additionally, the apparatus includes a current generation system.

Device and method for voltage regulator with stable and fast response and low standby current

A system and method for providing a voltage. The system includes a first transistor including a first gate, a first terminal, and a second terminal. The first terminal is configured to receive a first predetermined voltage, and the first gate is configured to receive a first control signal. Additionally, the system includes a second transistor including a second gate, a third terminal, and a fourth terminal. The second gate is configured to receive a second control signal, the third terminal is biased to a second predetermined voltage, the second terminal and the fourth terminal are directly connected to a first node, and the first node is associated with a first voltage level. Moreover, the system includes a third transistor including a third gate, a fifth terminal, and a sixth terminal.

System and method for switching between high voltage and low voltage

A system and method for adaptively providing a power supply voltage. The system includes an input/output subsystem configured to receive a first voltage, an analog subsystem configured to receive a second voltage and coupled to the input/output subsystem, a first digital subsystem configured to receive a third voltage and coupled to the input/output subsystem, and a second digital subsystem configured to receive a fourth voltage and coupled to the input/output subsystem, the first digital subsystem, and the analog subsystem.

System and method for providing adaptive power supply to system on a chip

A system and method for adaptively providing a power supply voltage. The system includes an oscillator configured to receive an output voltage and generate a firs signal. The first signal is associated with a first frequency and a first period. Additionally, the system includes a frequency comparator configured to receive the first signal associated with the first frequency and a second signal associated with a second frequency and to generate a third signal if the first frequency and the second frequency are not equal, and a voltage regulator coupled to the frequency comparator and configured to generate the output voltage based on at least information associated with the third signal. The output voltage is received by a powered system, and the powered system is configured to receive a clock signal associated with a clock frequency. The clock frequency is equal to the second frequency.

System and method for adaptive power supply to reduce power consumption

An apparatus and method for generating differential signals. The apparatus includes a first operational amplifier receiving a first signal, a second operational amplifier receiving a second signal, and a first transistor. The first transistor includes a first gate, a first terminal, and a second terminal. Additionally, the apparatus includes a second transistor. The second transistor includes a second gate, a third terminal, and a fourth terminal. Moreover, the apparatus includes a first resistor coupled to the first terminal and the third terminal, and a second resistor coupled to the second terminal and the fourth terminal. Also, the apparatus includes a first current supplier coupled to the first terminal, a second current supplier coupled to the second terminal, a third current supplier coupled to the third terminal, and a fourth current supplier coupled to the fourth terminal.

High bandwidth apparatus and method for generating differential signals

An apparatus and method for providing a reference voltage for regulating voltage levels. The apparatus includes a first voltage generation system configured to receive a first control signal and output a calibration voltage, a voltage adjustment system configured to receive the calibration voltage and a reference voltage and output a second control signal, and a second voltage generation system configured to receive the second control signal and output the reference voltage. The voltage adjustment system includes a latch system configured to receive a third control signal and a fourth control signal and output the first control signal.

A system and method for providing a voltage. The system includes a first transistor with a first gate, a first terminal, and a second terminal, a second transistor with a second gate, a third terminal, and a fourth terminal, and a third transistor with a third gate, a fifth terminal, and a sixth terminal. Additionally, the system includes a fourth transistor with a fourth gate, a seventh terminal, and an eighth terminal, a fifth transistor with a fifth gate, a ninth terminal, and a tenth terminal, and a sixth transistor with a sixth gate, an eleventh terminal, and a twelfth terminal. The tenth terminal and the eleventh terminal are directly connected at a third node, which is directly connected to a first substrate for the third transistor, a second substrate for the fourth transistor, a third substrate for the fifth transistor, and a fourth substrate for the sixth transistor.

A system and method for adaptively providing a power supply voltage. The system includes an input/output subsystem configured to receive a first voltage, an analog subsystem configured to receive a second voltage and coupled to the input/output subsystem, a first digital subsystem configured to receive a third voltage and coupled to the input/output subsystem, and a second digital subsystem configured to receive a fourth voltage and coupled to the input/output subsystem, the first digital subsystem, and the analog subsystem. Additionally, the system includes a first adaptive power supply configured to receive an input voltage and generate the third voltage, and a second adaptive power supply configured to receive the input voltage and generate the fourth voltage.

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Shanghai, China

Wenzhe Luo