Intel Corporation

Wenyin Fu

Abhishek R Appu

Altug Koker

Kamal Sinha

Joydeep Ray

Bhushan M Borole

Prasoonkumar Surti

Balaji Vembu

Travis T Schluessler

Linda L Hurd

Nikos Kaburlasos

Josh B Mastronarde

Subramaniam M Maiyuran

Adam T Lake

Jeffery S Boles

John H Feit

Narayan Srinivasa

Justin E Gottschlich

Karthik Vaidyanathan

Feng Chen

Eriko Nurvitadhi

Sara S Baghsorkhi

Ben J Ashbaugh

Nicolas C Galoppo Von Borries

Rajkishore Barik

Dukhwan Kim

Nadathur Rajagopalan Satish

Devan Burke

Tsung-Han Lin

Farshad Akhbari

Kiran Chand Veernapu

Ankur N Shah

Eric J Hoekstra

Anupama Ambardar Thaploo

Vasanth Ranganathan

Kai Xiao

Abhishek Venkatesh

Jacek Kwiatkowski

Elmoustapha Ould-Ahmed-Vall

Deepak Shashidhar Vembar

Jonathan Kennedy

Iqbal Rajwani

Sanjeev S Jahagirdar

Guei-Yuan Lueh

Michael Apodaca

Atsuo Kuwahara

David M Puffer

Aravindh V Anantaraman

Chandrasekaran Sakthivel

James A Valerio

Pattabhiraman K

Philip R Laws

Brent E Insko

Tomasz Janczak

Saurabh Sharma

David M Cimini

Radhakrishnan Venkataraman

Slawomir Grajewski

Eric J Asperheim

Anupreet S Kalra

Hugues Labbe

Sunil Nekkanti

Bee Ngo

Eric C Samson

Jaydeep P Kulkarni

Hughes Labbe

Pradeep K Golconda

Shalini Sankar

In one embodiment, a processor includes: a graphics processor to execute a workload; and a power controller coupled to the graphics processor. The power controller may include a voltage ramp circuit to receive a request for the graphics processor to operate at a first performance state having a first operating voltage and a first operating frequency and cause an output voltage of a voltage regulator to increase to the first operating voltage. The voltage ramp circuit may be configured to enable the graphics processor to execute the workload at an interim performance state having an interim operating voltage and an interim operating frequency when the output voltage reaches a minimum operating voltage. Other embodiments are described and claimed.

System, apparatus and method for increasing performance in a processor during a voltage ramp

Embodiments provide mechanisms to facilitate compute operations for deep neural networks. One embodiment comprises a graphics processing unit comprising one or more multiprocessors, at least one of the one or more multiprocessors including a register file to store a plurality of different types of operands and a plurality of processing cores. The plurality of processing cores includes a first set of processing cores of a first type and a second set of processing cores of a second type. The first set of processing cores are associated with a first memory channel and the second set of processing cores are associated with a second memory channel.

Compute optimization mechanism for deep neural networks

Methods and apparatus relating to techniques for avoiding cache lookup for cold cache. In an example, an apparatus comprises logic, at least partially comprising hardware logic, to collect user information for a user of a data processing device, generate a user profile for the user of the data processing device from the user information, and set a power profile a processor in the data processing device using the user profile. Other embodiments are also disclosed and claimed.

Processor power management

In an example, an apparatus comprises a plurality of execution units comprising at least a first type of execution unit and a second type of execution unit and logic, at least partially including hardware logic, to analyze a workload and assign the workload to one of the first type of execution unit or the second type of execution unit. Other embodiments are also disclosed and claimed.

Hybrid low power homogenous grapics processing units

Methods and apparatus relating to techniques for provision of low power foveated rendering to save power on GPU (Graphics Processing Unit) and/or display are described. In various embodiment, brightness/contrast, color intensity, and/or compression ratio applied to pixels in a fovea region are different than those applied in regions surrounding the fovea region. Other embodiments are also disclosed and claimed.

Low power foveated rendering to save power on GPU and/or display

An apparatus to facilitate compute optimization is disclosed. The apparatus includes one or more processing units to provide a first set of shader operations associated with a shader stage of a graphics pipeline, a scheduler to schedule shader threads for processing, and a field-programmable gate array (FPGA) dynamically configured to provide a second set of shader operations associated with the shader stage of the graphics pipeline.

An embodiment of a graphics apparatus may include a processor, memory communicatively coupled to the processor, and a collaboration engine communicatively coupled to the processor to identify a shared graphics component between two or more users in an environment, and share the shared graphics components with the two or more users in the environment. Embodiments of the collaboration engine may include one or more of a centralized sharer, a depth sharer, a shared preprocessor, a multi-port graphics subsystem, and a decode sharer. Other embodiments are disclosed and claimed.

Collaborative multi-user virtual reality

An apparatus to facilitate compute optimization is disclosed. The apparatus includes a plurality of processing units each comprising a plurality of execution units (EUs), wherein the plurality of EUs comprise a first EU type and a second EU type.

An apparatus to facilitate compute optimization is disclosed. The apparatus includes a plurality of processing units each comprising a plurality of processing cores of a first type and a second type. A first set of processing cores of a first type perform multi-dimensional matrix operations and a second set of processing cores of a second type perform general purpose graphics processing unit (GPGPU) operations.

A control surface tracks an individual cacheline in the original surface for frequent data values. If so, control surface bits are set. When reading a cacheline from memory, first the control surface bits are read. If they happen to be set, then the original memory read is skipped altogether and instead the bits from the control surface provide the value for the entire cacheline.

Frequent data value compression for graphics processing units

A hybrid hierarchical cache is implemented at the same level in the access pipeline, to get the faster access behavior of a smaller cache and, at the same time, a higher hit rate at lower power for a larger cache, in some embodiments. A split cache at the same level in the access pipeline includes two caches that work together. In the hybrid, split, low level cache (e.g., L1) evictions are coordinated locally between the two L1 portions, and on a miss to both L1 portions, a line is allocated from a larger L2 cache to the smallest L1 cache.

Replacement policies for a hybrid hierarchical cache

Growing community of inventors

Folsom, CA, United States of America

Wenyin Fu