Yangtze Memory Technologies Co., Ltd.

Wenxi Zhou

Zhiliang Xia

Kun Zhang

Zhong Zhang

Yuancheng Yang

Zongliang Huo

Di Wang

Linchun Wu

Lei Liu

Zhongwang Sun

Wei Liu

Liang Chen

Yanhong Wang

Tao Yang

ZongLiang Huo

Rui Su

DongXue Zhao

Qiguang Wang

Wei Xie

Tingting Zhao

Yuhui Han

Cuicui Kong

Lei Jin

Shan Li

Cheng Gan

Ziqun Hua

Yanwei Shi

Zhi Zhang

Jianzhong Wu

Jiwei Cheng

Bingguo Wang

Yueqiang Pu

Yingjie Ouyang

Dongxue Zhao

Bingjie Yan

Lichuan Zhao

Jingtao Xie

Yan Gu

Ling Xu

Yaqin Liu

A three-dimensional (3D) memory device includes a stack structure having interleaved conductive layers and dielectric layers, and a channel structure extending through the stack structure along a first direction. The channel structure is in contact with a source of the 3D memory device at a bottom portion of the channel structure. The channel structure includes a semiconductor channel, and a memory film over the semiconductor channel. The memory film includes a first angled structure, and a first diameter of the memory film at the bottom portion below the first angled structure is smaller than a second diameter of the memory film at an upper portion above the first angled structure.

Three-dimensional memory devices and methods for forming the same

Aspects of the disclosure provide a semiconductor device. The semiconductor device includes a stack structure and a contact structure. The stack structure comprises interleaved gate layers and insulating layers. The contact structure comprises a conductive structure and one or more insulating structures. The conductive structure can extend through the stack structure and form a conductive connection with one of the gate layers. The one or more insulating structures surround the conductive structure and electrically isolate the conductive structure from remaining ones of the gate layers. The one or more insulating structures further include one or more first insulating structures. Each of the one or more first insulating structures is disposed between an adjacent pair of the insulating layers, and the one or more first insulating structures are disposed on a first side of the one of the gate layers.

Vertical memory devices and method of fabrication thereof

Three-dimensional (3D) memory devices and methods for forming the same are disclosed. In certain aspects, a 3D memory device includes a first semiconductor assembly, a second semiconductor assembly, and an inter-assembly bonding layer between the first semiconductor assembly and the second semiconductor assembly. The first semiconductor assembly includes a first array structure and a first periphery structure. The first array structure includes a first memory stack having a plurality of interleaved stack conductive layers and stack dielectric layers. The first periphery structure includes a plurality of first peripheral circuits electrically connected to the first memory stack. The second semiconductor assembly includes a second array structure and a second periphery structure. The second array structure includes a second memory stack having a plurality of interleaved stack conductive layers and stack dielectric layers. The second periphery structure includes a plurality of second peripheral circuits electrically connected to the second memory stack.

Three-dimensional memory devices having semiconductor assemblies bonded by bonding layer and methods for forming the same

The present disclosure relates to a three-dimensional (3D) memory and a fabrication method thereof. The method includes forming a memory chip on a first substrate, disposing a first semiconductor layer on the memory chip, forming a plurality of first contacts through the first semiconductor layer, forming a first peripheral circuit chip based on the first semiconductor layer, disposing a second semiconductor layer on the first peripheral circuit chip, forming a plurality of second contacts through the second semiconductor layer, and forming a second peripheral circuit chip based on the second semiconductor layer. The first peripheral circuit chip is electrically connected with the memory chip through the plurality of first contacts, and the second peripheral circuit chip is electrically connected with the memory chip through the plurality of first and second contacts.

Three-dimensional memory and fabrication method thereof

Embodiments of three-dimensional memory devices are disclosed. A disclosed memory structure can comprises a memory cell, a bit line contact coupled to the memory cell, a bit line coupled to the bit line contact, a source line contact coupled to the memory cell, and a source line coupled to the source line contact. The memory cell comprises a cylindrical body having a cylindrical shape, an insulating layer surrounding the cylindrical body, a word line contact surrounding a first portion of the insulating layer, the word line contact coupled to a word line, and a plurality of plate line contact segments surrounding a second portion of the insulating layer, the plurality of plate line contact segments coupled to a common plate line.

Three-dimensional memory devices having a cylindrical body and plate line contact segments

A three-dimensional (3D) memory device includes a memory cell, a top contact coupled to the memory cell, and a bottom contact coupled to the memory cell. The memory cell can include a pillar, an insulating layer surrounding the pillar, a first gate contact coupled to a word line, a second gate contact coupled to a plate line, and an annular dielectric layer within a portion of the pillar. The annular dielectric layer can increase a retention time of electrical charge in the pillar. The 3D memory device can utilize dynamic flash memory (DFM), increase retention times, decrease refresh rates, increase a floating body effect, decrease manufacturing defects, decrease leakage current, decrease junction current, decrease power consumption, increase an upper limit of charge density in the pillar, dynamically adjust a length of the plate line, and decrease parasitic resistance.

Dynamic flash memory (DFM) with ring-type insulator in channel for improved retention

In certain aspects, a method for forming a three-dimensional (3D) memory device is disclosed. A stack structure including interleaved first dielectric layers and second dielectric layers is formed. Channel structures extending through the first dielectric layers and the second dielectric layers in a first region of the stack structure are formed. All the second dielectric layers in the first region and parts of the second dielectric layers in a second region of the stack structure are replaced with conductive layers. Word line pick-up structures extending through the first dielectric layers and remainders of the second dielectric layers in the second region of the stack structure are formed at different depths, such that the word line pick-up structures are electrically connected to the conductive layers, respectively, in the second region of the stack structure.

A three-dimensional (3D) memory device includes a stack structure having interleaved conductive layers and dielectric layers, and a channel structure extending through the stack structure along a first direction. The channel structure is in contact with a source of the 3D memory device at a bottom portion of the channel structure. The channel structure includes a semiconductor channel, and a memory film over the semiconductor channel. The memory film includes a tunneling layer over the semiconductor channel, a storage layer over the tunneling layer, and a blocking layer over the storage layer. A first thickness of the bottom portion of the channel structure is larger than a second thickness of a top portion of the channel structure.

The present disclosure provides a method for forming a three-dimensional (3D) memory device. The method includes forming an alternating dielectric stack on a substrate, wherein the alternating dielectric stack includes a plurality of dielectric layer pairs, each dielectric layer pair comprising a first dielectric layer and a second dielectric layer different from the first dielectric layer. The method also includes forming a staircase structure in the alternating dielectric stack and disposing an insulating layer on the staircase structure and the alternating dielectric stack. The method further includes forming an embedded hard mask on the insulating layer, wherein the embedded hard mask includes two or more sets of patterns configured to form two or more sets of vertical structures that are fabricated sequentially. The two or more sets of patterns are embedded in the 3D memory device.

Three-dimensional NAND memory and fabrication method thereof

Aspects of the disclosure provide a semiconductor device including a stack structure and a first conductive pillar. The stack structure can include a plurality of interlayer insulating layers and gate layers arranged alternately along a stack direction, and stack structure an array region and a staircase region adjoining the array region. The stack structure has a plurality of staircases in the staircase region arranged corresponding to the gate layers. Each of the gate layers can include a first gate part at the corresponding staircase and a second gate part connected to the first gate part, and a thickness of the first gate part along the stack direction is less than that of the second gate part along the stack direction. The first conductive pillar is arranged in the staircase region and penetrates through the stack structure along the stack direction, and the first conductive pillar is electrically connected with the first gate part.

Semiconductor device and its manufacturing method, memory and memory system

A method for forming a three-dimensional (3D) memory device is disclosed. An array of NAND memory strings is formed on a first substrate. A first semiconductor layer is formed above the array of NAND memory strings. The first semiconductor layer includes single crystalline silicon. A first transistor is formed on the first semiconductor layer. A second semiconductor layer is formed above the first transistor. The second semiconductor layer includes single crystalline silicon. A second transistor is formed on the second semiconductor layer.

Methods for forming three-dimensional memory devices

Embodiments of three-dimensional memory devices and fabricating methods thereof are disclosed. One disclosed method for forming a memory structure comprises: forming a bottom conductive layer on a substrate; forming a memory stack on the bottom conductive layer, the memory stack comprising a plurality of alternatively arranged dielectric layers and conductive layers; forming an opening penetrating the memory stack and exposing the bottom conductive layer; forming a cap layer on a bottom of the opening; forming a cylindrical body and a top contact on the cap layer and in the opening; and forming a plurality of interconnection structures to electrically connect the bottom conductive layer, the plurality of conductive layers of the memory stack, and the top contact.

Three-dimensional memory devices and fabricating methods thereof

Embodiments of three-dimensional (3D) memory devices and methods for forming the same are disclosed. In an example, a method for forming a 3D memory device comprises forming a channel structure extending vertically through a memory stack into a semiconductor layer on a substrate. The memory stack comprises interleaved stack conductive layers and stack dielectric layers. The method further comprises forming an insulating structure in an opening extending vertically through the memory stack and at a distance away from the channel structure, and comprising a dielectric layer doped with at least one of hydrogen or an isotope of hydrogen.

Methods for forming three-dimensional memory device

The present disclosure provides a method for forming a three-dimensional (3D) memory device. The method includes forming a dielectric stack on a substrate, and forming a first opening penetrating through the dielectric stack and extending into the substrate from a first side of the dielectric stack. The method also includes forming a first layer and a second layer inside the first opening from the first side of the dielectric stack, wherein the first layer covers a sidewall and a bottom of the first opening. The method further includes removing a portion of the first layer located at the bottom of the first opening from a second side of the dielectric stack to expose a portion of the second layer. The method further includes forming a second semiconductor layer from the second side of the dielectric stack to contact the exposed portion of the second layer.

Method of fabricating three-dimensional NAND memory

In certain aspects, a three-dimensional (3D) memory device includes a first semiconductor structure, a second semiconductor structure, and a bonding interface between the first and second semiconductor structures. The first semiconductor structure includes an array of NAND memory strings, a first peripheral circuit of the array of NAND memory strings including a first transistor, a polysilicon layer between the array of NAND memory strings and the first peripheral circuit, and a first semiconductor layer in contact with the first transistor. The polysilicon layer is in contact with sources of the array of NAND memory strings. The second semiconductor structure includes a second peripheral circuit of the array of NAND memory strings including a second transistor, and a second semiconductor layer in contact with the second transistor. The second semiconductor layer is between the bonding interface and the second peripheral circuit. The polysilicon layer is between the first semiconductor layer and the second semiconductor layer.

Growing community of inventors

Wuhan, China

Wenxi Zhou